Datasheet

DS32EL0124, DS32ELX0124
www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013
Addr (Hex) Name Bits Field R/W Default Description
20 Device Config 7 LVDS Always On Clock R/W 0 1: Disable
0 0: When not locked switch to Always On
Clock
6:3 Reserved 0
2 Reverse Data Order R/W 0 0: Normal
1: Reverse output data order
1 Reset Channel R/W 0 Reset input high speed channel
0 Digital Power Down R/W 0 Power down parallel, seria-to-parallell, and
always on clock
21 Device Config 7 Reserved 0
1
6 NRZI Decode Enable R/W 0 Enable NRZI decoding of incoming data;
requires an override bit
5 Descramble Enable R/W 0 Enabled the descrambler, requires an
override bit
4 Rx Mux R/W 0 RX_MUX_SEL control register. requires an
override bit
3 Decode Bypass R/W 0 Bypass DC Balance decoder. requires an
override bit
2 Training Sequence R/W 0 Enable training sequence. requires an
Enable override bit
1:0 Device Configuartion R/W 0 MSB: Remote Sense enable, active low
LSB: DC balance encoder enable, active low
requires an override bit
22 Device Config 7 Reserved 0
Override
6 NRZ Override R/W 0 Unlock bit 6 of register 21'h
5 Descramble Override R/W 0 Unlock bit 5 of register 21'h
4 Rx Mux Override R/W 0 Unlock bit 4 of register 21'h
3 Reserved 0
2 Decode Bypass Override R/W 0 Unlock bit 3 of register 21'h
1 Traning Override R/W 0 Unlock bit 2 of register 21'h
0 Device Config Override R/W 0 Unlock bits 1 and 0 of register 21'h
23 — 26 Reserved
27 LVDS Per 7 LVDS V
OD
High R/W 0 0: LVDS V
OD
normal operation. Setting used
Channel in Electrical Characteristics Table
Enable 1: Increases V
OD
. Allows for longer traces to
be driven, but consume more power
6 LVDS Control R/W 0 1: Allow SMBus to control LVDS per channel
enable
5 RxCLKOUT Enable R/W 0 Enables RxCLKOUT output driver
4 RxOUT4 Enable R/W 0 Enables RxOUT4 output driver
3 RxOUT3 Enable R/W 0 Enables RxOUT3 output driver
2 RxOUT2 Enable R/W 0 Enables RxOUT2 output driver
1 RxOUT1 Enable R/W 0 Enables RxOUT1 output driver
0 RxOUT0 Enable R/W 0 Enables RxOUT0 output driver
28 LVDS Config 7 Reserved 0
6 LVDS Reset R/W 0 Resets LVDS block
5 LVDS Clock Rate R/W 1 0:RxCLKOUT is DDR/2
1: RxCLKOUT is DDR
4 LVDS Clock Invert R/W 0 Inverts the polarity of the RxCLKOUT signal
3:2 LVDS Clock Delay R/W 10'b 00: 160 ps
11: -80 ps
80 ps step size
1:0 Reserved 0
29 — 2A Reserved
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: DS32EL0124 DS32ELX0124