Datasheet

DS32EL0124, DS32ELX0124
SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com
Typical Performance Characteristics
The eye diagrams shown below illustrate the typical performance of the DS32ELX0124/DS32EL0124 configured with RS = 0,
DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an
LMK03000C to generate the various clock frequencies. The data was then sent to a DS32ELX0421 configured with RS = 0,
DC_B = 0, which transmitted the data across the specified cable type and length at the specified data rate. The signal
conditioning settings used for each measurement are also listed below the figures.
Figure 15. LVDS RxCLKOUT Output Figure 16. LVDS RxOUT0 Output
(1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, (1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting,
0x10 DS32EL0421 De-Emphasis setting) 0x10 DS32EL0421 De-Emphasis setting)
Figure 17. LVDS RxCLKOUT Output Figure 18. LVDS RxOUT0 Output
(3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ (3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ
setting, 0x10 DS32EL0421 De-Emphasis setting) setting, 0x10 DS32EL0421 De-Emphasis setting)
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