Datasheet

DS32EL0124, DS32ELX0124

SNLS284K –MAY 2008–REVISED APRIL 2013

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HIGH SPEED COMMUNICATION MEDIA

Using the deserializer’s integrated equalizer blocks in combination with the DS32EL0421 or DS32ELX0421’s

integrated de-emphasis block allows data to be transmitted across a variety of media at high speeds. Factors

that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy

components and poor layout techniques. Although many cables contain wires of similar gauge and shielding,

performance can vary greatly depending on the quality of the connector.

The DS32ELX0124 also has a programmable de-emphasis block on its retimed loop through output TxOUT+/-.

The de-emphasis setting for the loop through driver is programmed through the SMBus.

REDUNDANCY APPLICATIONS

The DS32ELX0124 has two high speed CML serial inputs. SMBus register control allows the host device to

monitor for errors or link loss on the active input channel. This enables the host device, usually an FPGA, to

switch to the secondary input if problems occur with the primary input.

LINK AGGREGATION

Multiple DS32EL0421/DS32ELX0421 serializers and D32EL0124/DS32ELX0124 deserializers can be

aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data

valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6,

DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps.

Link aggregation configurations can also be implemented in applications which require longer cable lengths. In

these type of applications the data rate of each serializer and deserializer chipset can be reduced, such that the

applications' net data throughput is still the same. Since each high speed channel is now operating at a fraction

of the original data rate, the loss over the cable is reduced, allowing for greater lengths of cable to be used in the

system.

For more information regarding link aggregation please see Application Note 1887, Expanding the Payload with

TI's FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer.

REACH EXTENSION

The DS32ELX0124 deserializer contains a retimed loop through CML serial output. The loop through driver also

has programmable de-emphasis making this device capable of reach extension applications.

DAISY CHAINING

The loop through driver of the DS32ELX0124 deserializer can be used to string together deserializers in a daisy

chain configuration. This allows a single data source such as a DS32EL0421 serializer to communicate to

multiple receiving systems.

LAYOUT GUIDELINES

It is important to follow good layout practices for high speed devices. The length of LVDS input traces should not

exceed 40 inches. In noisy environments the LVDS traces may need to be shorter to prevent data corruption due

to EMI. Noisy components should not be placed next to the LVDS or CML traces. The LVDS and CML traces

must have a controlled differential impedance of 100Ω. Do not place termination resistors at the CML inputs or

output, the DS32EL0124 and DS32ELX0124 have internal termination resistors. It is recommended to avoid

using vias. Each pair of vias creates an impedance mismatch in the transmission line and result in reflections,

which can greatly lower the maximum distance of the high speed data link. If vias are required, they should be

placed symmetrically on each side of the differential pair. For more tips and detailed suggestions regarding high

speed board layout principles, please consult the LVDS Owner’s Manual.

Product Folder Links: DS32EL0124 DS32ELX0124