Datasheet

Config Pins
(RS, DC_B)
NRZ Decoder Descrambler
Lane
Alignment
Logic
DC Balance
Decoder
Total
Propagation
Delay
Data Flow
1, 1
0, 0
0, 1
1, 0
2 clocks
2 clocks
2 clocks
2 clocks
1 clock
1 clock
1 clock
(bypassed)
1 clock
1 clock
1 clock
(bypassed)
3 clocks
3 clocks
3 clocks
3 clocks
1 clock
1 clock
3-4 clocks
3-4 clocks
3-4 clocks
3-4 clocks
9-10 clocks
11-12 clocks
10-11 clocks
LVDS
Interface
CML Interface
10-11 clocks
DS32EL0124, DS32ELX0124
www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013
PROPAGATION DELAY
Once the deserializer is locked, the amount of time it takes for a signal to travel from the high speed CML serial
input through the device and out via the DDR LVDS interface is defined to be the propagation delay. The
propagation delay through the DS32EL0124/DS32ELX0124 due to the analog circuitry is considered negligible
compared to the time delay caused by the digital components. The information presented in this section allows
system designers to predict the propagation delay through the device in terms of clock cycles which are
proportional to the high speed serial line rate.
Each clock cycle shown inFigure 13 is defined to be 1/20
th
of the high speed serial bit rate. For example, at a
serial line rate of 3.125 Gbps the clock frequency of each delay cycle would be 156.25 MHz. Note, this is not the
same frequency as the LVDS outputs, which would be 312.5 MHz for a serial line rate of 3.125 Gbps. Dashed
lines in Figure 13 indicate that the feature is disabled by default in that mode and therefore add no more time to
the total propagation delay. In the last row, bypassed indicates that the data is sampled even though the feature
is disabled by default. The sampling of the data results in an added amount of propagation delay as specified in
the box.
Figure 13. Deserializer Propagation Delay
PROPAGATION DELAY FOR RETIMED LOOP THROUGH DRIVER — DS32ELX0124 ONLY
If the loop through driver is enabled in the DS32ELX0124, the propagation delay can also be defined as the
amount of time it takes a signal to pass from the high speed CML serial input to the retimed loop through driver
output. This time delay is measured in CDR clock cycles. The CDR clock frequency is equal to high speed serial
line rate or one high speed serial bit width. For example, if the high speed serial line rate is 3.125 Gbps, then the
CDR clock frequency is 3.125 GHz. The propagation delay from the high speed input to the loop through driver
output is 1 CDR clock.
Applications Information
GPIO PINS
The GPIO pins can be useful tools when debugging or evaluating the system. For specific GPIO configurations
and functions refer to registers 2, 3, 4, 5 and 6 in the device register map.
GPIO pins are commonly used when there are multiple deserializers on the same SMBus. In order to program
individual settings into each serializer, they will each need to have a unique SMBus address. To reprogram
multiple deserializers on a single SMBus, configure the first deserializer such that the SMBus lines are connected
to the FPGA or host controller. The CS pin of the second serializer should be tied to GPIO0 of the first
deserializer, with the CS pin of the next deseriazlier tied to GPIO0 of its preceding deserializer. By holding all of
the GPIO0 pins low, the first deserializer’s address may now be reprogrammed by writing to register 0. The first
deserializer’s GPIO pin can now be asserted and the second deserializer’s address may now be reprogrammed.
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