Datasheet

DS32EL0124, DS32ELX0124
SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com
When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane
alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. In
this mode the deserializer locks to incoming random data. To achieve lock during the clock acquisition phase, the
incoming data should have a transition density of approximately 20% for a period of 200 µs. Scrambling and
NRZI encoding can be implemented to help improve the transition density of the data. This pin setting also allows
for the devices to interface with other active components in the high speed signal path.
Table 2. Device Configuration Table
Remote Sense Pin (RS) DC-Balance Pin (DC_B) Configuration
0 0 Remote Sense enabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder disabled by default
0 1 Remote Sense enabled
DC-Balance disabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1 0 Remote Sense disabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
1 1 Remote Sense disabled
DC-Balance disabled
No Data Alignment
De-Scrambler and NRZI decoder disabled by default
SMBus INTERFACE
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the SMB_CS pin HIGH enables the SMBus port, allowing access to the
configuration registers. Holding the SMB_CS pin LOW disables the device's SMBus, allowing communication
from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains
active. When communication to other devices on the SMBus is active, the SMB_CS signal for the deserializer
must be driven LOW.
The address byte for all DS32EL0124 and DS32ELX0124 devices is B0'h. Based on the SMBus 2.0
specification, these devices have a 7-bit slave address of 1011000'b. The LSB is set to 0'b (for a WRITE), thus
the 8-bit value is 1011 0000'b or B0'h.
The SCK and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SCK is HIGH.
There are three unique states for the SMBus:
START A HIGH to LOW transition on SDA while SCK is HIGH indicates a message START condition.
STOP A LOW to HIGH transition on SDA while SCK is HIGH indicates a message STOP condition.
IDLE If SCK and SDA are both HIGH for a time exceeding t
BUF
from the last detected STOP condition or if they are HIGH for a total
exceeding the maximum specification for t
HIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
The devices support WRITE and READ transactions. See Register Map for register address, type (Read/ Write,
Read Only), default value and function information.
Writing to a Register
The devices support WRITE and READ transactions. See Register Map for register address, type (Read/ Write,
Read Only), default value and function information.
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Product Folder Links: DS32EL0124 DS32ELX0124