Datasheet

DS32EL0124, DS32ELX0124
www.ti.com SNLS284K –MAY 2008–REVISED APRIL 2013
CML INPUT INTERFACING
The DS32ELX0124 has two inputs to support redundancy and failover applications. Either input can be selected
by using the RX_MUX_SEL pin or internal control registers. Whichever input is selected will be routed to the
CDR of the deserializer. Only one input may be selected at a time. Within the CDR, the data is strobed at the
center of the eye diagram(i.e. 0.5UI).
The input stage is self-biased and does not need any external bias circuitry. The DS32EL0124 and
DS32ELX0124 include integrated input termination resistors. These deserializers also support a wide common
mode input from 50mV to Vcc - 50mV and can be DC-coupled where there is no significant Ground potential
difference between the interfacing systems. The serial inputs also provides input equalization control in order to
compensate for loss from the media. The level of equalization is controlled by the SMBus interface. For the
DS32ELX0124, each input can have its own independent equalizer settings.
It is recommended to use RxIN0+/- as the primary input. Due to its close proximity to the loop through driver,
RxIN1 has a typical performance less than RxIN0, with regards to cable length performance. When interfacing to
RxIN1+/- and transmitting with the loop through driver on TxOUT+/-, it is important to follow good layout practices
as described in the LAYOUT GUIDELINES section and in the LVDS Owner’s Manual. Poor layout techniques
can result in excessive cross talk coupled into RxIN1.
CML OUTPUT INTERFACING (DS32ELX0124 ONLY)
The retimed loop through serial outputs of the DS32ELX0124 provide low-skew differential signals. Internal
resistors connected from TxOUT+ and TxOUT- to VDD25 terminate the outputs. The output level can be set by
adjusting the pull-down resistor to the VOD_CTRL pin. The output terminations can also be programmed to be
either 50 or 75 ohms.
The output buffer consists of a current mode logic(CML) driver with user configurable de-emphasis control, which
can be used to optimize performance over a wide range of transmission line lengths and attenuation distortions
resulting from low cost CAT(-5, -6, -7) cable or FR4 backplane. Output de-emphasis is user programmable
through SMBus interface. Users can control the strength of the de-emphasis to optimize for a specific system
environment. Please see the Register Map, register 67'h bits 6:5, for details.
DEVICE CONFIGURATION
There are four ways to configure the DS32EL0124 and DS32ELX0124 devices, these combinations are shown in
Table 2. Refer to Figure 9 to see how the combinations of the RS and DC_B pins change the link startup
behavior of the deserializers. When connecting to a serializer other than the DS32EL0421 or DS32ELX0421,
Remote Sense should be disabled. The descrambler and NRZI decoder shown in Table 2 can be enabled or
disabled through register programming.
When Remote Sense is enabled, with RS pin tied low, the deserializer must be connected directly to a
DS32EL0421/DS32ELX0421 serializer without any active components between them. The Remote Sense
module features both an upstream and downstream communication method for the serializer to detect a
deserializer and vice versa. This feature is used to pass link status information between the 2 devices.
If DC-Balance is enabled, the maximum number of parallel LVDS lanes is four. The fifth lane becomes a Data
Valid signal (TXIN4±). If the Data Valid input to the serializer is logic high, then SYNC characters are transmitted.
If the deserializer receives a SYNC character, then the LVDS data outputs will all be logic low and the Data Valid
outputs will be logic high. If the deserializer detects a DC-Balance code error, the output data pins will be set to
logic high with the Data Valid output also set to logic high.
In the case where DC-Balance is enabled and Remote Sense is disabled, with RS set to high and DC_B set to
low, an external device should toggle the Data Valid input to the serializer periodically to ensure constant lock.
With these pin settings the devices can interface with other active component in the high speed signal path, such
as fiber modules. Every time a DS32EL0421/DS32ELX0421 serializer establishes a link to a
DS32EL0124/DS32ELX0124 deserializer with DC-Balance enabled and Remote Sense disabled, the Data Valid
input to the serializer must be held high for 110 LVDS clock periods. This allows the deserializer to extract the
clock and perform lane alignment while skipping the LINK ACQUISITION state.
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Product Folder Links: DS32EL0124 DS32ELX0124