Datasheet

DS32EL0124, DS32ELX0124
SNLS284K –MAY 2008–REVISED APRIL 2013 www.ti.com
FUNCTIONAL DESCRIPTION
POWER SUPPLIES
The DS32EL0124 and DS32ELX0124 have several power supply pins, at 2.5V as well as 3.3V. It is important
that these pins all be connected and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF
capacitors as a minimum, with a 0.1μF capacitor on each power pin. A 22 μF capacitor is required on the
VDDPLL pin which is connected to the 3.3V rail.
These devices have a large contact in the center on the bottom of the package. This contact must be connected
to the system GND as it is the major ground connection for the device.
POWER UP
It is recommended, although not necessary, to bring up the 3.3V power supply before the 2.5V supply. If the 2.5V
supply is powered up first, an initial current draw of approximately 600mA from the 2.5V rail may occur before
settling to its final value. Regardless of the sequence, both power rails should monotonically ramp up to their final
values.
POWER MANAGEMENT
These devices have two methods to reduce power consumption. To enter the first power save mode, the on
board host FPGA or controlling device can cease to output the DDR transmit clock. To further reduce power, a
write to the power down register will put the device in its lowest power mode.
RESET
There are three ways to reset these devices. A reset occurs automatically during power-up. The device can also
be reset by pulling the RESET pin low, with normal operation resuming when the pin is driven high again. The
device can also be reset by writing to the reset register. This reset will put all of the register values back to their
default values, except it will not affect the address register value if the SMBus default address has been
changed.
LVDS OUTPUTS
The DS32EL0124 and DS32ELX0124 has standard LVDS outputs, compatible with ANSI/TIA/EIA-644. It is
recommended that the PCB trace between the FPGA and the deserializer output be no more than 40-inches.
Longer PCB traces may introduce signal degradation as well as channel skew which could cause serialization
errors. The connection between the host and the DS32EL0124 or DS32ELX0124 should be over a controlled
impedance transmission line with impedance that matches the termination resistor – usually 100Ω. Setup and
hold times are specified in the LVDS Switching Characteristics table, however the clock delay can be adjusted by
writing to register 30’h.
LOOP FILTER
The DS32EL0124 and DSELX0124 have an internal clock data recovery module (CDR), which is used to recover
the input serial data. The loop filter for this CDR is external, and for optimum results, a 30nF capacitor should be
connected between pins 26 and 27. See the Typical Interface Circuit (Figure 14).
LOOP THROUGH DRIVER LAUNCH AMPLITUDE
The launch amplitude of the retimed CML loop through driver is controlled by placing a single resistor from the
VOD_CTRL pin to ground. Use the following equation to obtain the desired V
LTOD
by selecting the corresponding
resistor value.
R = (1400 mV / V
LTOD
) x 9.1 kΩ (1)
The retimed CML loop through driver launch amplitude can also be adjusted by writing to SMBus register 49'h,
bits 3:1. This register is meant to assist system designers during the initial prototype design phase. For final
production, it is recommended that the appropriate resistor value be selected for the desired V
LTOD
and that
register 49'h be left to its default value.
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