Datasheet

DS26LV31T
www.ti.com SNLS114C –MARCH 1999–REVISED FEBRUARY 2013
Electrical Characteristics
(1) (2)
Over supply voltage and operating temperature ranges, unless otherwise specified
Parameter Test Conditions Pin Min Typ Max Units
V
OD1
Output Differential Voltage R
L
= ∞ (No Load) DO+, 3.3 4 V
DO−
V
OD2
Output Differential Voltage R
L
= 100Ω (Figure 2) 2 2.6 V
ΔV
OD2
Change in Magnitude of I
O
≥ 20 mA
−400 7 400 mV
Output Differential Voltage
V
OD3
Output Differential Voltage R
L
= 3900Ω (V.11) 3.2 3.6 V
Figure 2 and
(3)
V
OC
Common Mode Voltage R
L
= 100Ω (Figure 2) 1.5 2 V
ΔV
OC
Change in Magnitude of
−400 6 400 mV
Common Mode Voltage
I
OZ
TRI-STATE Leakage V
OUT
= V
CC
or GND
±0.5 ±20 μA
Current Drivers Disabled
I
SC
Output Short Circuit Current V
OUT
= 0V T
A
= -40°C to +85°C −40 −70 −150 mA
V
IN
= V
CC
or
T
A
= -55°C to -30 -160 mA
GND
(4)
+125°C
(5)
I
OFF
Output Leakage Current V
CC
= 0V, V
OUT
= 3V or 6V 0.03 100 μA
V
CC
= 0V, V
OUT
= T
A
= -40°C to +85°C −0.08 −100 μA
−0.25V
T
A
= -55°C to -200 μA
+125°C
V
IH
High Level Input Voltage DI, 2.0 V
CC
V
V
IL
Low Level Input Voltage EN, GND 0.8 V
I
IH
High Level Input Current V
IN
= V
CC
EN* 10 μA
I
IL
Low Level Input Current V
IN
= GND −10 μA
V
CL
Input Clamp Voltage I
IN
= −18 mA −1.5 V
I
CC
Power Supply Current No Load, V
IN
(all) = V
CC
T
A
= -40°C to +85°C V
CC
100 μA
or GND
T
A
= -55°C to 125 μA
+125°C
(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except differential voltages V
OD1
, V
OD2
, V
OD3
.
(2) All typicals are given for V
CC
= +3.3V, T
A
= +25°C.
(3) This specification limit is for compliance with TIA/EIA-422-B and ITU-T V.11.
(4) Only one output shorted at a time. The output (true or complement) is configured High.
(5) This parameter does not meet the TIA/EIA-422-B specification.
Switching Characteristics - Industrial
(1) (2)
Over supply voltage and -40°C to +85°C operating temperature range, unless otherwise specified
Parameter Test Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low R
L
= 100Ω, C
L
= 50 pF
6 10.5 16 ns
(Figure 3 and Figure 4)
t
PLHD
Differential Propagation Delay Low to High 6 11 16 ns
t
SKD
Differential Skew (same
0.5 2.0 ns
channel) |t
PHLD
− t
PLHD
|
t
SK1
Skew, Pin to Pin (same device) 1.0 2.0 ns
t
SK2
Skew, Part to Part
(3)
3.0 5.0 ns
t
TLH
Differential Transition Time
4.2 10 ns
Low to High (20% to 80%)
t
THL
Differential Transition Time
4.7 10 ns
High to Low (80% to 20%)
t
PHZ
Disable Time High to Z (Figure 5 Figure 6) 12 20 ns
t
PLZ
Disable Time Low to Z 9 20 ns
(1) f = 1 MHz, t
r
and t
f
≤ 6 ns, 10% to 90%.
(2) See TIA/EIA-422-B specifications for exact test conditions.
(3) Devices are at the same V
CC
and within 5°C within the operating temperature range
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