Datasheet

DS26C32AM, DS26C32AT
SNLS382C –JUNE 1998–REVISED APRIL 2013 www.ti.com
Figure 7. Propagation Delay for “LS-Type” Load
(1) Diagram shown for ENABLE low.
(2) S1 and S2 of load circuit are closed except where shown.
(3) Pulse generator for all pulses: Rate ≤ 1.0 MHz; Z
O
= 50Ω; t
r
≤ 15 ns; t
f
≤ 6.0 ns.
Figure 8. Enable and Disable Times for “LS-Type” Load
Truth Table
(1)
ENABLE ENABLE Input Output
L H X Z
All Other V
ID
≥ V
TH
(Max) H
Combinations of
V
ID
≤ V
TH
(Min) L
Enable Inputs
Open H
(1) Z = TRI-STATE
TYPICAL APPLICATIONS
Figure 9. Two-Wire Balanced Systems, RS-422
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