Datasheet

DS25BR440

www.ti.com

SNLS258B –FEBRUARY 2008–REVISED MARCH 2013

PIN DESCRIPTIONS

Pin Name I/O, Type Pin Description

Number

IN0+, IN0- , 1, 2, I, LVDS Inverting and non-inverting high speed LVDS input pins.

IN1+, IN1-, 4, 5,

IN2+, IN2-, 6, 7,

IN3+, IN3- 9, 10

OUT0+, OUT0-, 29, 28, O, LVDS Inverting and non-inverting high speed LVDS output pins.

OUT1+, OUT1-, 27, 26,

OUT2+, OUT2-, 24, 23,

OUT3+, OUT3- 22, 21

EQ0, EQ1, 40, 39, I, LVCMOS Receive equalization level select pins.

EQ2, EQ3 11, 12

PE0, PE1, 31, 20, I, LVCMOS Transmit pre-emphasis level select pins.

PE2, PE3 19, 18

PWDN0, 35, I, LVCMOS Channel output power down pins. When the PWDNn is set to L, the channel

PWDN1, 34, output OUTn is in the power down mode. The LOS circuitry on the

PWDN2, 33, corresponding input remains enabled.

PWDN3 32

LOS0, LOS1, 14, 37, O, LVCMOS Loss Of Signal output pins, LOSn report when an open input fault condition is

LOS2, LOS3 36, 13 detected at the input, INn. These are open drain outputs. External pull up

resistors are required.

NC 17 NC NO CONNECT pins. May be left floating.

PWDN 38 I, LVCMOS Device power down pin. When the PWDN is set to L, the device is in the

power down mode. The LOS circuitry is disabled as well.

VDD 3, 8, Power Power supply pins.

15,25, 30

GND 16, DAP Power Ground pin and a pad (DAP - die attach pad).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS25BR440