Datasheet

OUT+
OUT-
DS25BR440
Receiver
IN+
IN-
100: Differential T-Line
100:
LVDS
Driver
DS25BR440
SNLS258B –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
Test Channel Length Insertion Loss (dB)
(inches)
500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz
A 10 -1.2 -1.7 -2.0 -2.4 -2.7 -2.8
B 20 -2.6 -3.5 -4.1 -4.8 -5.5 -5.6
C 30 -4.3 -5.7 -7.0 -8.2 -9.4 -9.7
D 15 -1.6 -2.2 -2.7 -3.2 -3.7 -3.8
E 30 -3.4 -4.5 -5.6 -6.6 -7.7 -7.9
F 60 -7.8 -10.3 -12.4 -14.5 -16.6 -17.0
Functional Description
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over
lossy FR-4 printed circuit board backplanes and balanced cables.
The DS25BR440 has a pre-emphasis control pin for each output for switching the transmit pre-emphasis to ON
and OFF setting and an equalization control pin for each input for switching the receive equalization to ON and
OFF setting. The following are the transmit pre-emphasis and receive equalization truth tables.
Table 1. Transmit Pre-Emphasis Truth Table
(1)
OUTPUT OUTn, n = {0, 1, 2, 3}
CONTROL Pin (PEn) State Pre-emphasis Level
0 OFF
1 ON
(1) Transmit Pre-emphasis Level Selection for an Output OUTn
Table 2. Receive Equalization Truth Table
(1)
INPUT INn, n = {0, 1, 2, 3}
CONTROL Pin (EQn) State Equalization Level
0 OFF
1 ON
(1) Receive Equalization Level Selection for an Input INn
Input Interfacing
The DS25BR440 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25BR440 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25BR440 inputs are internally terminated with a 100Ω resistor.
Figure 10. Typical LVDS Driver DC-Coupled Interface to an DS25BR440 Input
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR440