Datasheet

DS25BR204

www.ti.com

SNLS259D –NOVEMBER 2007–REVISED MARCH 2013

PIN DESCRIPTIONS

Pin Name I/O, Type Pin Description

Number

IN1+, IN1-, 4, 5, I, LVDS Inverting and non-inverting high speed LVDS input pins.

IN2+, IN2-, 6, 7,

OUT0+, OUT0-, 29, 28, O, LVDS Inverting and non-inverting high speed LVDS output pins.

OUT1+, OUT1-, 27, 26,

OUT2+, OUT2-, 24, 23,

OUT3+, OUT3- 22, 21

EQ1, EQ2, 39,11 I, LVCMOS Receive equalization level select pins.

PE0, PE1, 31, 20, I, LVCMOS Transmit pre-emphasis level select pins.

PE2, PE3 19, 18

SEL_in 14 I, LVCMOS Input select pin.

LOS2 36, O, LVCMOS Loss of Signal output pin, LOSn, reports when an open input fault condition is

LOS1 37 detected at the input, INn. These are open drain outputs. External pull up

resistors are required.

PWDN0, 35, I, LVCMOS Channel output power down pins. When the PWDNn is set to L, the channel

PWDN1, 34, output, OUTn, is in the power down mode.

PWDN2, 33,

PWDN3 32

NC 1, 2, NC NO CONNECT pins. May be left floating.

9, 10,

12, 13,

17, 40

PWDN 38 I, LVCMOS Device power down pin. When the PWDN is set to L, the device is in the

power down mode.

VDD 3, 8, Power Power supply pins.

15,25, 30

GND 16, DAP Power Ground pin and a pad (DAP - die attach pad).

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS25BR204