Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers LVDS 3.125 GBit/s LLP 40 EP

ASIC/FPGA

ASIC/FPGA 1

CARD A CARD C

BACKPLANE

DS25BR204

1:4 LVDS

Repeater

Discrete

Serializer

ASIC/FPGA 2

Discrete

Deserializer 1

Discrete

Deserializer 2

CARD B

DS25BR204

www.ti.com

SNLS259D –NOVEMBER 2007–REVISED MARCH 2013

DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive

Equalization

Check for Samples: DS25BR204

FEATURES

DESCRIPTION

The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater

• DC - 3.125 Gbps Low Jitter, Low Skew, Low

optimized for high-speed signal routing and switching

Power Operation

over lossy FR-4 printed circuit board backplanes and

• Pin Selectable Transmit Pre-Emphasis and

balanced cables. Fully differential signal paths ensure

Receive Equalization Eliminate Data

exceptional signal integrity and noise immunity.

Dependant Jitter

The device has two different LVDS input channels

• Wide Input Common Mode Range Allows DC-

and a select line determines which input is active.

coupled Interface to LVDS, CML and LVPECL

Both inputs have programmable equalization

Drivers

providing maximum signal strength. A loss-of-signal

(LOS) circuit monitors both input channels and a

• Redundant Inputs

unique LOS pin reports when no signal is detected at

• Integrated 100Ω Input and Output

that input.

Terminations

Wide input common mode range allows the switch to

• 8 kV ESD on LVDS I/O Pins Protects Adjoining

accept signals with LVDS, CML and LVPECL levels;

Components

the output levels are LVDS. A very small package

• Small 6 mm x 6 mm WQFN-40 Space Saving

footprint requires a minimal space on the board while

Package

the flow-through pinout allows easy board layout.

Each differential input and output is internally

APPLICATIONS

terminated with a 100Ω resistor to lower device return

losses, reduce component count and further minimize

• Clock and Data Distribution

board space.

• Clock and Data Buffering and Muxing

• OC-48 / STM-16

• SD/HD/3GHD SDI Routers

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 DS25BR204 3.125 Gbps 1:4 LVDS Repeater with Transmit Pre-Emphasis and Receive Equalization Check for Samples: DS25BR204 FEATURES DESCRIPTION • The DS25BR204 is a 3.125 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and switching over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. 1 2 • • • • • • DC - 3.
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DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.
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DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 PIN DESCRIPTIONS Pin Name Pin Number IN1+, IN1-, IN2+, IN2-, I/O, Type Pin Description 4, 5, 6, 7, I, LVDS Inverting and non-inverting high speed LVDS input pins. OUT0+, OUT0-, OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3- 29, 27, 24, 22, O, LVDS Inverting and non-inverting high speed LVDS output pins. EQ1, EQ2, 39,11 I, LVCMOS Receive equalization level select pins.
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DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage LVCMOS Input Voltage −0.3V to (VCC + 0.3V) LVCMOS Output Voltage −0.3V to (VCC + 0.3V) −0.3V to +4V LVDS Input Voltage Differential Input Voltage |VID| 1V −0.3V to (VCC + 0.3V) LVDS Output Voltage LVDS Differential Output Voltage 0.
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DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 Electrical Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (2) (3) Symbol Parameter Conditions IIL Low Level Input Current VIN = GND VCC = 3.6V VCL Input Clamp Voltage ICL = −18 mA, VCC = 0V VOL Low Level Output Voltage IOL= 4 mA Min Typ Max Units 0 ±10 μA −0.9 −1.5 V 0.
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DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.
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DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 AC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol tDJ1D tDJ2D tTJ1D tTJ2D Parameter Conditions tRJ2BD tDJ2BD tTJ2BD Units 2.5 Gbps 17 30 ps 3.125 Gbps 15 28 ps Total Jitter (Peak to Peak) Test Channel D VID = 350 mV VCM = 1.2V PRBS-23 (NRZ) 2.5 Gbps 0.07 0.13 UIP-P 3.125 Gbps 0.08 0.
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DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Figure 4. LVDS Output Transition Times Pre-Emphasis and Equalization Test Circuits DS25BR204 CHARACTERIZATION BOARD 50: Microstrip 50: Microstrip ¼ DS25BR204 L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 5.
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DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 TEST CHANNEL DS25BR204 CHARACTERIZATION BOARD 50: Microstrip TEST CHANNEL 50: Microstrip ¼ DS25BR204 L=4" L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50: Microstrip 50: Microstrip Figure 8. Pre-Emphasis and Equalization Performance Test Circuit 50: MS 50: MS L = A, B or C L=1" L=1" L=1" 50: MS L=1" 100: Diff. Stripline 50: MS Figure 9.
PAGE 10
DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com The DS25BR204 has a pre-emphasis control pin for each output for switching the transmit pre-emphasis to ON and OFF setting and an equalization control pin for each input for switching the receive equalization to ON and OFF setting. The following are the transmit pre-emphasis and receive equalization truth tables. Table 2.
PAGE 11
DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 12. Typical LVPECL Driver DC-Coupled Interface to an DS25BR204 Input Output Interfacing The DS25BR204 outputs signals are compliant to the LVDS standard. Its outputs can be DC-coupled to most common differential receivers.
PAGE 12
DS25BR204 SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance 60 150 VCC = 3.3V TA = 25°C 50 NRZ PRBS-7 EQ = Off 40 PE = Off TA = 25°C NRZ PRBS7 EQ = On 125 RESIDUAL JITTER (ps) TOTAL JITTER (ps) VCC = 3.3V 30 20 10 100 20" FR4 Stripline 75 50 25 0 10" FR4 Stripline 0 0 0.8 1.6 2.4 3.2 0 4.0 0.8 DATA RATE (Gbps) 2.4 3.2 4.0 DATA RATE (Gbps) Figure 14. Total Jitter as a Function of Data Rate Figure 15.
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DS25BR204 www.ti.com SNLS259D – NOVEMBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS25BR204TSQ/NOPB WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 DS25BR204TSQX/NOPB WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS25BR204TSQ/NOPB WQFN RTA DS25BR204TSQX/NOPB WQFN RTA 40 250 213.0 191.0 55.0 40 2500 367.0 367.0 38.
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MECHANICAL DATA RTA0040A SQA40A (Rev B) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.