Datasheet
EQ0
IN+
IN-
EQ1
VCC
OUT+
OUT-
NC
1
2
3
4
8
6
5
7
GND
DAP
OUT+
OUT-
EQ0
IN+
IN-
EQ1
DS25BR110
SNLS255E –MARCH 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
Pin Diagram
Pin Descriptions
Pin
Type Description
Name Number
EQ0 1 Input Equalizer select pin.
IN+ 2 Input Non-inverting LVDS input pin.
IN- 3 Input Inverting LVDS input pin.
EQ1 4 Input Equalizer select pin.
NC 5 NA "NO CONNECT" pin.
OUT- 6 Output Inverting LVDS output pin.
OUT+ 7 Output Non-inverting LVDS Output pin.
VCC 8 Power Power supply pin.
GND DAP Power Ground pad (DAP - die attach pad)
Control Pins (EQ0 and EQ1) Truth Tables
EQ1 EQ0 Equalization Level
0 0 Off
0 1 Low (Approx. 4 dB at 1.56 GHz)
1 0 Medium (Approx. 8 dB at 1.56 GHz)
1 1 High (Approx. 16 dB at 1.56 GHz)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR110