Datasheet

DS16EV5110A
www.ti.com SNLS301C –JULY 2008–REVISED APRIL 2013
9. The Device drives the 8-bit data value (register contents).
10. The Host drives a NACK bit “1”indicating end of the READ transfer.
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS signal Low.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see Table 1 for more information.
Table 1. SMBus Register Descriptions
Name Address Default Type
(1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Status 0x00 0x00 RO ID Revision Reserved Reserved Reserve SD
d
Status 0x01 0x00 RO Reserved Boost 1 EN Reserved
Status 0x02 0x00 RO Reserved Boost 3 Reserved Boost 2
Internal 0x03 0x77 RW EN (Int.) Boost Control EN (Int.) Reserved
Enable/ 0:Enable (BC for CH0) 0:Enable
Individual 1:Disable 000 (Min Boost) 1:Disable
Channel (D_IN0±) 001 (C_IN±)
Boost 010
Control 011
for 100
C_IN±, 101
D_IN0± 110
111 (Max Boost)
Individual 0x04 0x77 RW EN (Int.) Boost Control EN (Int.) Boost Control
Channel 0:Enable (BC for CH2) 0:Enable (BC for CH1)
Boost 1:Disable 000 (Min Boost) 1:Disable 000 (Min Boost)
Control (D_IN2±) 001 (D_IN1±) 001
for 010 010
D_IN1±, 011 011
D_IN2± 100 100
101 101
110 110
111 (Max Boost) 111 (Max Boost)
Signal 0x05 0x00 RW Reserved Threshold (mV)
Detect ON
00: 70 (Default)
(SD_ON)
01: 55
10: 90
11: 75
Signal 0x06 0x00 RW Reserved Threshold (mV)
Detect OFF
00: 40 (Default)
(SD_OFF)
01: 30
10: 55
11: 45
SMBus 0x07 0x00 RW Reserved SMBus
orCMOS Enable
Control for 0: Disable
EN 1: Enable
Output 0x08 0x78 RW Reserved Output Level: Reserved
Level 00: 540 mVp-p
01: 770 mVp-p
10: 1000 mVp-p
11: 1200 mVp-p
(1) Note: RO = Read Only, RW = Read/Write
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