Datasheet
DAP = GND
DS16EV5110ASQ
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
D_IN2+
D_IN2-
D_IN1+
D_IN1-
D_IN0+
D_IN0-
C_IN+
C_IN-
D_OUT2+
D_OUT2-
D_OUT1+
D_OUT1-
D_OUT0+
D_OUT0-
C_OUT+
C_OUT-
VDD
VDD
VDD
VDD GND
GND
GND
GND
VDD
VDD
GND
GND
BST_1
BST_0
CS
SDC
SDA
Reserv
VDD
SD
EN
Reserv
Reserv
Reserv
Reserv
Reserv
Reserv
Reserv
BST_2
Reserv
FEB
Reserv
DS16EV5110A
www.ti.com
SNLS301C –JULY 2008–REVISED APRIL 2013
PIN DESCRIPTIONS (continued)
Pin Name Pin Number I/O
(1)
, Type Description
System Management Bus (SMBus) Interface Control Pins
SDA 18 IO, LVCMOS SMBus Data Input / Output. Internally pulled High to 3.3V with High-Z pull up.
SDC 17 I, LVCMOS SMBus Clock Input. Internally pulled High to 3.3V with High-Z pull up.
CS 16 I, LVCMOS SMBus Chip select. When held High, the equalizer SMBus register is enabled. When held
Low, the equalizer SMBus register is disabled. CS is internally pulled Low. CS is internally
gated with SDC.
Other
Reserv 19, 20, 38, Reserved. Do not connect.
39, 40,41,
42, 43, 47,
48
Connection Diagram
TOP VIEW — Not to Scale
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS16EV5110A