Datasheet
DS15MB200
SNLS196E –NOVEMBER 2005–REVISED MARCH 2013
www.ti.com
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol Parameter Conditions Min Typ
(1)
Max Units
LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n)
V
IH
High Level Input Voltage 2.0 V
DD
V
V
IL
Low Level Input Voltage GND 0.8 V
I
IH
High Level Input Current V
IN
= V
DD
= V
DDMAX
−10 +10 µA
I
IHR
High Level Input Current PREA_n, PREB_n, PREL_n 40 200 µA
I
IL
Low Level Input Current V
IN
= V
SS
, V
DD
= V
DDMAX
−10 +10 µA
C
IN1
Input Capacitance Any Digital Input Pin to V
SS
2.0 pF
C
OUT1
Output Capacitance Any Digital Output Pin to V
SS
4.0 pF
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 −0.8 V
LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±)
V
TH
Differential Input High Threshold
(2)
V
CM
= 0.8V or 1.2V or 3.55V,
0 100 mV
V
DD
= 3.6V
V
TL
Differential Input Low Threshold
(2)
V
CM
= 0.8V or 1.2V or 3.55V,
−100 0 mV
V
DD
= 3.6V
V
ID
Differential Input Voltage V
CM
= 0.8V to 3.55V, V
DD
= 3.6V 100 2400 mV
V
CMR
Common Mode Voltage Range V
ID
= 150 mV, V
DD
= 3.6V 0.05 3.55 V
C
IN2
Input Capacitance IN+ or IN− to V
SS
2.0 pF
I
IN
Input Current V
IN
= 3.6V, V
DD
= V
DDMAX
or 0V −15 +15 µA
V
IN
= 0V, V
DD
= V
DDMAX
or 0V −15 +15 µA
LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±)
V
OD
Differential Output Voltage, R
L
is the internal 100Ω between OUT+
250 360 500 mV
0% Pre-emphasis
(2)
and OUT−
ΔV
OD
Change in V
OD
between
-35 35 mV
Complementary States
V
OS
Offset Voltage
(3)
1.05 1.22 1.475 V
ΔV
OS
Change in V
OS
between
-35 35 mV
Complementary States
I
OS
Output Short Circuit Current OUT+ or OUT− Short to GND −21 -40 mA
C
OUT2
Output Capacitance OUT+ or OUT− to GND when TRI-
4.0 pF
STATE
SUPPLY CURRENT (Static)
I
CC
Supply Current All inputs and outputs enabled and
active, terminated with external load of 225 275 mA
100Ω between OUT+ and OUT-.
I
CCZ
Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0 = ENA_1 =
0.6 4.0 mA
ENB_1 = ENL_1 = L
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200
170 250 ps
Time Mb/s, measure between 20% and 80% of
V
OD
.
(4)
t
HLT
Differential High to Low Transition
170 250 ps
Time
t
PLHD
Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200
1.0 2.5 ns
Delay Mb/s, measure at 50% V
OD
between
input to output.
t
PHLD
Differential High to Low Propagation
1.0 2.5 ns
Delay
t
SKD1
Pulse Skew |t
PLHD
–t
PHLD
|
(4)
25 75 ps
t
SKCC
Output Channel to Channel Skew Difference in propagation delay (t
PLHD
or
50 115 ps
t
PHLD
) among all output channels.
(4)
(1) Typical parameters are measured at V
DD
= 3.3V, T
A
= 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage V
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
ID
is defined as ABS(IN+–IN−).
(3) Output offset voltage V
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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