Datasheet
R
L
OUT+
OUT-
IN+
IN-
Signal Generator
1/4 DS15BR400
R D
R D
R
L
V
OH
V
OL
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
1/4 DS15BR400
DS15BR400, DS15BR401
SNLS224G –AUGUST 2006–REVISED APRIL 2013
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol Parameter Conditions Min Max Units
(1)
t
JIT
Jitter (0% Pre-emphasis) RJ - Alternating 1 and 0 at 750 MHz
(6)
0.5 1.5 ps
(5)
DJ - K28.5 Pattern, 1.5 Gbps
(7)
14 30 ps
TJ - PRBS 2
23
-1 Pattern, 1.5 Gbps
(8)
14 31 ps
t
ON
LVDS Output Enable Time Time from PWDN to OUT± change from TRI-STATE to active.
20 µs
Figure 9, Figure 10
t
OFF
LVDS Output Disable Time Time from PWDN to OUT± change from active to TRI-STATE.
12 ns
Figure 9, Figure 10
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = V
ID
= 500 mV, input common mode voltage = V
ICM
= 1.2V, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps
(20% to 80%).
(7) Deterministic Jitter, or DJ, is a peak to peak value. Stimulus and fixture jitter has been subtracted. The input voltage = V
ID
= 500 mV,
input common mode voltage = V
ICM
= 1.2V, K28.5 pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%). The K28.5 pattern is repeating bit
streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = V
ID
= 500 mV, input common mode voltage = V
ICM
= 1.2V, 2
23
-1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50
ps (20% to 80%).
DC Test Circuits
Figure 5. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
Figure 6. Differential Driver AC Test Circuit
Figure 7. Propagation Delay Timing Diagram
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