Datasheet

DS15BR400, DS15BR401
www.ti.com SNLS224G –AUGUST 2006–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Typ
Symbol Parameter Conditions Min Max Units
(1)
LVDS INPUT DC SPECIFICATIONS (INn±)
V
TH
Differential Input High V
CM
= 0.8V to 3.55V,
0 100 mV
Threshold
(2)
V
DD
= 3.6V
V
TL
Differential Input Low V
CM
= 0.8V to 3.55V,
−100 0 mV
Threshold
(2)
V
DD
= 3.6V
V
ID
Differential Input Voltage V
CM
= 0.8V to 3.55V, V
DD
= 3.6V 100 2400 mV
V
CMR
Common Mode Voltage Range V
ID
= 150 mV, V
DD
= 3.6V 0.05 3.55 V
C
IN2
LVDS Input Capacitance IN+ or IN− to V
SS
3.0 pF
I
IN
Input Current V
IN
= 3.6V, V
DD
= 3.6V −10 +10 µA
V
IN
= 0V, V
DD
= 3.6V −10 +10 µA
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V
OD
Differential Output Voltage, R
L
= 100Ω external resistor between OUT+ and OUT−
250 360 500 mV
0% Pre-emphasis
(2)
Figure 5
ΔV
OD
Change in V
OD
between
−35 35 mV
Complementary States
V
OS
Offset Voltage
(3)
1.05 1.18 1.475 V
ΔV
OS
Change in V
OS
between
−35 35 mV
Complementary States
C
OUT
LVDS Output Capacitance OUT+ or OUT− to V
SS
2.5 pF
I
OS
Output Short Circuit Current OUT+ or OUT− Short to GND −21 −40 mA
OUT+ or OUT− Short to VDD 6 40 mA
SUPPLY CURRENT (Static)
I
CC
Supply Current All inputs and outputs enabled and active, terminated with
175 215 mA
differential load of 100Ω between OUT+ and OUT-. PEM = L
I
CCZ
Supply Current - Power Down PWDN = L, PEM = L
20 200 µA
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
LHT
Differential Low to High Use an alternating 1 and 0 pattern at 200 Mbps, measure
170 250 ps
Transition Time
(4)
between 20% and 80% of V
OD
.
Figure 6 , Figure 8
t
HLT
Differential High to Low
170 250 ps
Transition Time
(4)
t
PLHD
Differential Low to High Use an alternating 1 and 0 pattern at 200 Mbps, measure at
1.0 2.0 ns
Propagation Delay 50% V
OD
between input to output.
Figure 6 , Figure 7
t
PHLD
Differential High to Low
1.0 2.0 ns
Propagation Delay
t
SKD1
Pulse Skew
(4)
|t
PLHD
–t
PHLD
| 10 60 ps
t
SKCC
Output Channel to Channel Difference in propagation delay (t
PLHD
or t
PHLD
) among all
25 75 ps
Skew
(4)
output channels.
t
SKP
Part to Part Skew
(4)
Common edge, parts at same temp and V
CC
550 ps
(2) Differential output voltage V
OD
is defined as ABS(OUT+–OUT−). Differential input voltage V
ID
is defined as ABS(IN+–IN−).
(3) Output offset voltage V
OS
is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
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