DS125BR401EVM User’s Guide User's Guide Literature Number: SNLU121 November 2012
User's Guide SNLU121 – November 2012 DS125BR401EVM Evaluation Kit The DS125BR401EVM – SMA evaluation kit provides a complete high band-width platform to evaluate the signal integrity and signal conditioning features of the Texas Instruments signal conditioning products – with Equalization and De-emphasis. SMA edge launch connectors are used as the input and the output connections for this evaluation board.
Features www.ti.com 1 Features • • • • • • • • • • • 4 Lane Repeater up to 12.5 Gbps Low 65 mW/channel power consumption, with option to power down unused channels Transparent management of link training protocol for PCIe, SAS, and 10G-KR Receive Equalization up to 30 dB at 12.5 Gbps Settable transmit de-emphasis driver to -12 dB Transmit output voltage control: 700 – 1300 mV Programmable via pin selection, EEPROM, or SMBus interface Single supply operation: VIN = 3.3V±10% or VDD = 2.
Features www.ti.com Figure 2. DS125BREVK REV.
4-Level IO Control www.ti.com 2 4-Level IO Control Many of the control pins on the DS125BR401 have more than two valid levels. Table 1 below shows how to access each of these levels with the switch banks on the back side of the EVM. Table 1.
Switch Connection Overview 3 www.ti.com Switch Connection Overview Table 2. Connection and Control Description Component Name J1 to J8 IN_B2+, IN_B3+, IN_A0+, IN_A1+, J9 to J16 OUT_B2+, OUT_B3+, OUT_A0+, OUT_A1+, IN_B2-, IN_B3-, IN_A0-, IN_A1-, High-speed differential inputs OUT_B2-, OUT_B3-, OUT_A0-, OUT_A1-, High-speed differential outputs J19 VIN or VDD DC Power - VIN or VDD to DS125BR401SQ J20 VIN or VDD Jumper – VIN or VDD to VIH power J17 SDA, SCL Optional SMBUS access pins.
Quick Start Guide www.ti.com 4 Quick Start Guide 1. Connect J19: VIN = 3.3V or VDD = 2.5V and GND. • For VIN = 3.3V: Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and float VDD at J19. • For VIN = 2.5V: Set SW7 pin1 (VDD_SEL) to the OFF positions (disable internal LDO regulator) and float VIN at J19. 2. Set jumper – J20 for VIH connection to VIN or VDD. 3. Connect 50 Ohm SMA cables to the board. • The input signals J5 to J12 can be connected from a pattern generator.
Quick Start Guide www.ti.com 5. Set the input equalization level. • For external pin mode control of the equalization level: • Set ENSMB = 0 (1kΩ to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF). • SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected. • Refer to Table 1 for information on the 3 switch settings for the 4 level input. Example: • Set EQB[1:0] with SW1 for the B bank of inputs (top 4 inputs of DS125BR401).
Quick Start Guide www.ti.com 6. Set the output VOD and De-emphasis level. • For external pin mode control for the VOD and De-emphasis level: • Set ENSMB = 0 (1kΩ to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF). • SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected. • Refer to Table 1 for information on the 3 switch settings for the 4 level input. Example: • Set DEMB[1:0] with SW5 for the B bank of outputs (top 4 outputs of DS125BR401).
SMBus Slave Mode of the EQ, VOD, and De-Emphasis level: 5 SMBus Slave Mode of the EQ, VOD, and De-Emphasis level: • • • • • 10 www.ti.com Set ENSMB = 1 (1kΩ to VIH) by using the SW2 (3-2-1) = (OFF-OFF-ON). Set SW4 pin1,2 to the ON position so the SMBUS signals are connected. Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line. Set the SW1 and SW5 for the AD[3:0] pins. AD[3:0]=0000 sets device slave address = B0’hex. Connect SDA, SCL and GND to J17.
Bill of Materials for DS125BR401EVM: www.ti.com 6 Bill of Materials for DS125BR401EVM: Table 6. DS125BR401EVM BOM Item Qty 1 1 C1 445-3448-1-ND C1608Y5V0J106Z CAP CER 10UF 6.3V Y5V 0603 2 1 C2 445-1322-1-ND C1608X5R0J105K CAP CER 1.0UF 6.3V X5R 0603 5 C3, C4, C5, C6, C7 445-4711-1-ND C0603X5R0J104M CAP CER .10UF 6.3V X5R 0201 4 16 C11, C14, C17, C20, C23, C26 587-2483-1-ND LMK063BJ224MP-F CAP CER .
Schematic for DS125BR401EVM: 7 www.ti.com Schematic for DS125BR401EVM: Figure 3. DS125BR401EVM Schematic Note: The DS125BR401 and DS125BR800 share a common EVM PCB Assembly.
EVM Layout www.ti.com 8 EVM Layout The following Figures show the DS125BR401EVM board layout. The EVM controls signal integrity functions via a combination of switches and jumpers. The DS125BR401 is very compact and low power. The QFN package offers an exposed thermal pad to enhance electrical and thermal performance. This must be soldered to the copper landing on the PWB. Figure 4. Top Assembly Layer Figure 5.
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