Datasheet

DS10BR254
www.ti.com SNLS260D –DECEMBER 2007–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin
Pin Name I/O, Type Pin Description
Number
IN1+, IN1-, 4, 5, I, LVDS Inverting and non-inverting high speed LVDS input pins.
IN2+, IN2-, 6, 7,
OUT0+, OUT0-, 29, 28, O, LVDS Inverting and non-inverting high speed LVDS output pins.
OUT1+, OUT1-, 27, 26,
OUT2+, OUT2-, 24, 23,
OUT3+, OUT3- 22, 21
SEL_in 14 I, LVCMOS This pin selects which LVDS input is active.
LOS1, 37, O, LVCMOS Loss Of Signal output pins, LOSn report when an open input fault condition is
LOS2 36 detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
PWDN0, 35, I, LVCMOS Channel output power down pin. When the PWDNn is set to L, the channel
PWDN1, 34 output OUTn is in the power down mode.
PWDN2, 33,
PWDN3 32
PWDN 38 I, LVCMOS Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
VDD 3, 8, Power Power supply pins.
15,25, 30
GND 16, DAP Power Ground pin and a pad (DAP - die attach pad).
NC 1, 2 NC NO CONNECT pins. May be left floating.
9, 10,
11, 12,
13, 17,
18, 19,
20, 31,
39, 40
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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