Datasheet

DS100BR410
SNLS326B –OCTOBER 2010–REVISED APRIL 2013 www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1)
Parameter Test Conditions Min Typ Max Units
Equalization
DJ1 Residual Deterministic Jitter V
TX
= 1.0 V
P-P
,
at 10.3125 Gbps 12 meter 30 AWG cable,
0.10 0.22 UI
P-P
EQ = 03F'h (BST[2:0] = 111),
PRBS-7 (2
7
-1) pattern.
(7)
DJ2 Residual Deterministic Jitter V
TX
= 1.0 V
P-P
,
at 6.0 Gbps 12 meter 30 AWG cable,
0.07 0.12 UI
P-P
EQ = 07F'h, PRBS-7 (2
7
-1) pattern.
(7)
Signal DETECT and ENABLE Timing
t
ZISD
Input OFF to ON detect — SD Response time measurement at
35 ns
Output High Response Time V
IN
to SD output, V
IN
= 800 mV
P-P
,
100 Mbps, 40” of 6 mil microstrip
t
IZSD
Input ON to OFF detect — SD
400 ns
FR4. Figure 4
Output Low Response Time
t
OZOED
EN High to Output ON Response Response time measurement at
150 ns
Time EN input to V
O
, V
IN
= 800 mV
P-P
,
100 Mbps, 40” of 6 mil microstrip
t
ZOED
EN Low to Output OFF Response
5 ns
FR4. Figure 5
Time
(7) Deterministic jitter is measured at the differential outputs (point C of Figure 1), minus the deterministic jitter before the test channel (point
A of Figure 1). Random jitter is removed through the use of averaging or similar means.
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
(1)
Parameter Test Conditions Min Typ Max Units
Serial Bus Interface DC Specifications
V
IL
Data, Clock Input Low Voltage 0.8 V
V
IH
Data, Clock Input High Voltage 2.1 V
DD
V
I
PULLUP
Current Through Pull-Up Resistor High Power Specification
4 mA
or Current Source
V
DD
Nominal Bus Voltage 2.375 3.6 V
I
LEAK-Bus
Input Leakage Per Bus Segment See
(2)
-200 +200 µA
I
LEAK-Pin
Input Leakage Per Device Pin -15 µA
C
I
Capacitance for SDA and SDC See
(2) (3)
10 pF
R
TERM
External Termination Resistance V
DD3.3
,
(2) (3)
2000 Ω
pull to V
DD
= 2.5V ± 5% OR 3.3V ±
V
DD2.5
,
(2) (3)
1000 Ω
10%
Serial Bus Interface Timing Specifications – (See Figure 6)
(4)(5)
F
SMB
Bus Operating Frequency 10 100 kHz
T
BUF
Bus Free Time Between Stop and
4.7 µs
Start Condition
T
HD:STA
Hold time after (Repeated) Start At I
PULLUP
, Max
Condition. After this period, the first 4.0 µs
clock is generated.
T
SU:STA
Repeated Start Condition Setup
4.7 µs
Time
T
SU:STO
Stop Condition Setup Time 4.0 µs
T
HD:DAT
Data Hold Time 300 ns
(1) Typical values represent most likely parametric norms at V
DD
= 2.5V, T
A
= 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2) Maximum termination voltage should be identical to the device supply voltage.
(3) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(4) Recommended value. Parameter not tested in production.
(5) Recommended maximum capacitance load per bus segment is 400pF.
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