Datasheet

DS100BR111
SNLS338E –JANUARY 2011–REVISED FEBRUARY 2013 www.ti.com
Table 9. SMBus Register Map (continued)
Register EEPROM
Address Bits Field Type Default Description
Name Reg Bit
0x07 Digital Reset 7 Reserved R/W 0x01 Set bit to 0
and Control
6 Reset Regs Self clearing reset for registers.
Writing a [1] will return register settings to default
values.
5 Reset SMBus Self clearing reset for SMBus master state
Master machine
4:0 Reserved Set bits to '0001b
0x08 Pin Override 7 Reserved R/W 0x00 Set bit to 0
6 Override Idle Yes [1]: Override by Channel - see Reg 0x13 and
Threshold 0x19
[0]: SD_TH pin control
5 Reserved Yes Set bit to 0
4 Override IDLE Yes [1]: Force IDLE by Channel - see Reg 0x0E and
0x15
[0]: Normal Operation
3 Reserved Yes Set bit to 0
2 Override Out Mode
[1]: Enable Output Mode control for individual
outputs. See register locations 0x10[6] and
0x17[6].
[0]: Disable - Outputs are kept in the normal
mode of operation allowing VOD and DE
adjustments.
1 Override DEM Yes
0 Reserved Yes Set bit to 0
0x0C CH A 7 Reserved R/W 0x00 Set bit to 0
Analog
6 Reserved Set bit to 0
Override 1
5 Reserved Set bit to 0
4 Reserved Set bit to 0
3:0 Reserved Set bits to 0000'b.
0x0D CH A 7:0 Reserved R/W 0x00 Set bits to 00'h.
Reserved
0x0E CH A 7:6 Reserved R/W 0x00 Set bits to 00'b.
Idle Control
5 Idle Auto Yes Auto IDLE value when override bit is set (reg
0x08 [4] = 1)
4 Idle Select Yes Force IDLE value when override bit is set (reg
0x08 [4] = 1)
3 Reserved Yes Set bit to 0.
2:0 Reserved Set bits to 0.
0x0F CH A 7:0 BOOST [7:0] R/W 0x2F Yes EQ Boost Default to 24 dB
EQ Setting See Table 2 for Information
0x10 CH A 7 Sel_scp R/W 0xED Yes [1]: Short Circuit Protection ON
Control 1 [0]: Short Circuit Protection OFF
6 Output Mode Yes [1]: Normal operation
[0]: 10G-KR operation
5:3 Reserved Yes Set bits to = 101'b
2:0 Reserved Yes Set bits to = 101'b
28 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS100BR111