Datasheet

DS100BR111
www.ti.com SNLS338E –JANUARY 2011–REVISED FEBRUARY 2013
Table 9. SMBus Register Map
Register EEPROM
Address Bits Field Type Default Description
Name Reg Bit
0x00 Device ID 7 Reserved R/W 0x00 set bit to 0
6:3 I2C Address [3:0] R [6:3] SMBus strap observation
2 EEPROM reading R 1: EEPROM Loading
done 0: EEPROM Done Loading
1 Reserved RWSC set bit to 0
0 Reserved RWSC set bit to 0
0x01 Control 1 7:6 Idle Control R/W 0x00 Yes Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
5:3 Reserved R/W Set bits to 0
2 LOS Select R/W LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
1:0 Reserved R/W Set bits to 00'b
0x02 Control 2 7 Reserved R/W 0x00 Set bit to 0
6 Reserved Set bit to 0
5 LOS override Yes LOS pin override enable (1);
Use Normal Signal Detection (0)
4 LOS override value Yes 1: Normal Operation
0: Output LOS
3 PWDN Inputs Yes 1: PWDN
0: Normal Operation
2 PWDN Oscillator Yes
1 Reserved
0 Reserved Yes Set bit to 0
0x04 Control 3 7:6 eSATA Mode R/W 0x00 Yes [7] Channel A (1)
Enable [6] Channel B (1)
5 TX_DIS Override 1: Override Use Reg 0x04[4:3]
Enable 0: Normal Operation - uses pin
4 TX_DIS Value 1: TX Disabled
Channel A 0: TX Enabled
3 TX_DIS Value
Channel B
2 Reserved Set bit to 0
1:0 EQ CONTROL [1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
0x05 CRC 1 7:0 CRC[7:0] R/W 0x00 Slave Mode CRC Bits
0x06 CRC 2 7 Disable EEPROM R/W 0x10 Disable Master Mode EEPROM Configuration
CFG
6:5 Reserved Set bits to 0
4 Reserved Yes Set bit to 1
3 CRC Slave Mode [1]: CRC Disable (No CRC Check)
Disable [0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED register
updates will NOT take effect until correct CRC
value is loaded
2:1 Reserved Set bits to 0
0 CRC Enable Slave CRC Trigger
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: DS100BR111