Datasheet

DS100BR111A
www.ti.com SNLS400C –JANUARY 2012–REVISED APRIL 2013
PIN DESCRIPTIONS
(1)(2)
Pin Name Pin Number I/O, Type Pin Description
Differential High Speed I/O's
INA+, INA- , 24, 23 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
INB+, INB-, 11, 12 termination resistor connects INx+ to VDD and INx- to VDD when enabled.
OUTA+, OUTA-, 7, 8 O,CML Inverting and non-inverting 50Ω driver outputs with de-emphasis. Compatible with
OUTB+, OUTB-, 20, 19 AC coupled CML inputs.
Control Pins
ENSMB 3 I, LVCMOS System Management Bus (SMBus) enable pin
Float Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
ENSMB = 1 (SMBUS MODE)
SCL 5 I, LVCMOS ENSMB Master or Slave mode
O, Open SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a
Drain clock output in Master mode.
SDA 4 I, LVCMOS, ENSMB Master or Slave mode
O, Open The SMBus bidirectional SDA pin is enabled. Data input or open drain (pull-down
Drain only) output.
AD0-AD3 10, 9, 2, 1 I, LVCMOS, ENSMB Master or Slave mode
Float SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
(4-Levels) slave address inputs. There are 16 addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device SMBus address.
(3)
READEN# 17 I, LVCMOS When using an External EEPROM, a transition from high to low starts the load
from the external EEPROM
DONE# 18 IO, LVCMOS, EEPROM Download Status
Float HIGH indicates Error / Still Loading
(4-Levels) LOW indicates download complete. No Error.
ENSMB = 0 (PIN MODE)
EQA0, EQA1 10, 9 I, LVCMOS, EQA/B, 0/1 control the level of equalization of each channel. The EQA/B pins are
EQB0, EQB1 1, 2 Float active only when ENSMB is de-asserted (LOW).
(4-Levels) When ENSMB goes high the SMBus registers provide independent control of each
lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs. Table 2
DEMA, DEMB 4, 5 IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins are only active when
Float ENSMB is de-asserted (LOW). Each of the 4 A/B channels have the same level
(4-Levels) unless controlled by the SMBus control registers. When ENSMB goes high the
SMBus registers provide independent control of each lane and the DEM pins are
converted to SMBUS SCL and SDA pins.
Table 3
TX_DIS 6 I, LVCMOS DS100BR111A
High = OUTA Enabled /OUTB Disabled
Low = OUTA/B Enabled
VOD_SEL 17 I, LVCMOS, VOD select.
Float High = (VOD = 950 mV / 1150 mV)
(4-Levels) Float = (VOD = 850 mV)
20K = (VOD = 1050 mV)
Low = (VOD = 575 mV)
(4)
See Table 4 for additional information.
(3)
VDD_SEL 16 I, Internal Enables the 3.3V to 2.5V internal regulator
Pull-up Low = 3.3 V Operation
Float = 2.5 V Operation
MODE 18 I, LVCMOS, Controls Device Mode of Operation
Float High = Continuous Talk (no output IDLE)
(4-Levels) Float = Slow OOB
20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of inactivity. SD
stays active.
Low = SAS Mode, Fast OOB
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Unless the
"Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode).
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
(3) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = B0'h
(4) DS100BR111A OUTA is limited to 575mV in pin mode
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