Datasheet

DS100BR111A
www.ti.com SNLS400C –JANUARY 2012–REVISED APRIL 2013
Table 8. SMBus Register Map (continued)
Register EEPROM
Address Bits Field Type Default Description
Name Reg Bit
0x04 Control 3 7:6 eSATA Mode R/W 0x00 Yes [7] Channel A (1)
Enable [6] Channel B (1)
5 TX_DIS Override 1: Override Use Reg 0x04[4:3]
Enable 0: Normal Operation - uses pin
4 TX_DIS Value 1: TX Disabled
Channel A 0: TX Enabled
3 TX_DIS Value
Channel B
2 Reserved Set bit to 0'b
1:0 Reserved Set bits to 00'b
0x05 CRC 1 7:0 CRC[7:0] R/W 0x00 Slave Mode CRC Bits
0x06 CRC 2 7 Disable EEPROM R/W 0x10 Disable Master Mode EEPROM Configuration
CFG
6:5 Reserved Set bits to 00'b
4 Reserved Yes Set bit to 1'b
3 CRC Slave Mode [1]: CRC Disable (No CRC Check)
Enable [0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED register
updates will NOT take effect until correct CRC
value is loaded
2:1 Reserved Set bits to 00'b
0 CRC Enable Slave CRC Trigger
0x07 Digital Reset 7 Reserved R/W 0x01 Set bit to 0'b
and Control
6 Reset Regs Self clearing reset for registers
Writing a [1] will return register settings to default
values.
5 Reset SMBus Self clearing reset for SMBus master state
Master machine
4:0 Reserved Set bits to 0001'b
0x08 Pin Override 7 Reserved R/W 0x00 Set bit to 0
6 Override Idle Yes [1]: Override by Channel - see Reg 0x13 and
Threshold 0x19
[0]: SD_TH pin control
5 Reserved Yes Set bit to 0'b
4 Override IDLE Yes [1]: Force IDLE by Channel - see Reg 0x0E and
0x15
[0]: Normal Operation
3 Reserved Yes Set bit to 0'b
2 Reserved Yes Set bit to 0'b
1 Override DEM Yes
0 Reserved Yes Set bit to 0'b
0x0C CH A 7 Reserved R/W 0x00 Set bit to 0'b
Analog
6 Reserved Set bit to 0'b
Override 1
5 Reserved Set bit to 0'b
4 Reserved Set bit to 0'b
3:0 Reserved Set bits to 000'b
0x0D CH A 7:0 Reserved R/W 0x00 Set bits to 00'h
Reserved
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