Datasheet

DS100BR111A
SNLS400C –JANUARY 2012–REVISED APRIL 2013 www.ti.com
Table 7. Single EEPROM Header + Register Map with Default Value (continued)
EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BIt 0
Address Byte
Description 4 Ovrd_LOS LOS_Value PDWN Inp PWDN Osc Reserved eSATA eSATA Ovrd TX_DIS
Enable A Enable B
Register 0x02 [5] 0x02 [4] 0x02 [3] 0x02 [2] 0x02 [0] 0x04 [7] 0x04 [6] 0x04 [5]
Value 0 0 0 0 0 0 0 0
Description 5 TX_DIS CHA TX_DIS CHB Reserved Reserved Reserved Reserved Overide Reserved
IDLE_th
Register 0x04 [4] 0x04 [3] 0x04 [2] 0x04 [1] 0x04 [0] 0x06 [4] 0x08 [6] 0x08 [5]
Value 0 0 0 0 0 1 0 0
Description 6 Ovrd_IDLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register 0x08 [4] 0x08 [3] 0x08 [2] 0x08 [1] 0x08 [0] 0x0B [6] 0x0B [5] 0x0B [4]
Value 0 0 0 0 0 1 1 1
Description 7 Reserved Reserved Reserved Reserved Idle auto A Idle sel A Reserved Reserved
Register 0x0B [3] 0x0B [2] 0x0B [1] 0x0B [0] 0x0E [5] 0x0E [4] 0x0E [3] 0x0E [2]
Value 0 0 0 0 0 0 0 0
Description 8 CHA EQ[7] CHA EQ[6] CHA EQ[5] CHA EQ[4] CHA EQ[3] CHA EQ[2] CHA EQ[1] CHA EQ[0]
Register 0x0F [7] 0x0F [6] 0x0F [5] 0x0F [4] 0x0F [3] 0x0F [2] 0x0F [1] 0x0F [0]
Value 0 0 1 0 1 1 1 1
Description 9 A Sel scp Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register 0x10 [7] 0x10 [6] 0x10 [5] 0x10 [4] 0x10 [3] 0x10 [2] 0x10 [1] 0x10 [0]
Value 1 1 1 0 1 1 0 1
Description 10 DEMA[2] DEMA[1] DEMA[0] CHA Slow IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0]
Register 0x11 [2] 0x11 [1] 0x11 [0] 0x12 [7] 0x12 [3] 0x12 [2] 0x12 [1] 0x12 [0]
Value 0 1 0 0 0 0 0 0
Description 11 Idle auto B Idle sel B Reserved Reserved CHB EQ[7] CHB EQ[6] CHB EQ[5] CHB EQ[4]
Register 0x15 [5] 0x15 [4] 0x15 [3] 0x15 [2] 0x16 [7] 0x16 [6] 0x16 [5] 0x16 [4]
Value 0 0 0 0 0 0 1 0
Description 12 CHB EQ[3] CHB EQ[2] CHB EQ[1] CHB EQ[0] B Sel scp Reserved Reserved Reserved
Register 0x16 [3] 0x16 [2] 0x16 [1] 0x16 [0] 0x17 [7] 0x17 [6] 0x17 [5] 0x17 [4]
Value 1 1 1 1 1 1 1 0
Description 13 Reserved Reserved Reserved Reserved CHB DEM[2] CHB DEM[1] CHB DEM[0] CHB Slow
Register 0x17 [3] 0x17 [2] 0x17 [1] 0x17 [0] 0x18 [2] 0x18 [1] 0x18 [0] 0x19 [7]
Value 1 1 0 1 0 1 0 0
Description 14 IDLE thA[1] IDLE thA[0] IDLE thD[1] IDLE thD[0] Reserved Reserved Reserved Reserved
Register 0x19 [3] 0x19 [2] 0x19 [1] 0x19 [0]
Value 0 0 0 0 0 0 0 0
Description 15 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register
Value 0 0 1 0 1 1 1 1
Description 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register
Value 1 0 1 0 1 1 0 1
Description 17 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register
Value 0 1 0 0 0 0 0 0
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