Datasheet

INA+
INA-
OUTB+
VDD_SEL
VIN
18
INB+
INB-
17
14
13
16
LOS
VOD_SEL / READEN#
MODE / DONE#
SD_TH
OUTA+
OUTA-
OUTB-
SMBUS AND
CONTROL
15
VDD
24
23
22
21
20
19
11
12
8
10
9
7
EQB1/AD2
ENSMB
1
2
5
6
3
SCL/DEMB
EQB0/AD3
SDA/DEMA
4
VDD
TX_DIS
AD1/EQA1
AD0/EQA0
IN+
IN-
EQ
IDLE DETECT
OUTBUF
SMBus
VOD/ DE-EMPHASIS CONTROL
VDD
SMBus
Tx IDLE Enable
DEM
EQ[1:0]
OUT+
OUT-
50:50:
VOD
SMBus
LOS
Channel
Status
and
Control
SD_TH
TX_DIS
MODE
ASIC/FPGA
ASIC/FPGA
Interconnect
Cable
DS100BR111A
DS100BR111A
DS100BR111A
SNLS400C JANUARY 2012REVISED APRIL 2013
www.ti.com
Typical Application
Block Diagram - Detail View Of Channel (1 Of 2)
Pin Diagram
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Figure 1. DS100BR111A Pin Diagram 24 lead
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Product Folder Links: DS100BR111A