Datasheet

DS100BR111A
SNLS400C –JANUARY 2012–REVISED APRIL 2013 www.ti.com
NOTE
Settings are approximate and will change based on PCB material, trace dimensions, and
driver waveform characteristics.
Table 3. De-emphasis and Output Voltage Settings
Level VOD_SEL DEMA/B SMBus Register DEM Level SMBus Register VOD Level VOD (mV) DEM (dB)
1 0 0 000 000 575 0
2 0 Float 010 000 575 - 3.5
3 0 R 011 000 575 - 6
4 0 1 101 000 575 - 9
5 Float 0 000 011 850 0
6 Float Float 010 011 850 - 3.5
7 Float R 011 011 850 - 6
8 Float 1 101 011 850 - 9
9 R 0 000 101 1050 - 0
10 R Float 010 101 1050 - 3.5
11 R R 011 101 1050 - 6
12 R 1 101 101 1050 - 9
13 1 0 000 100 950 0
14 1 Float 001 100 950 - 1.5
15 1 R 001 110 1150 - 1.5
16 1 1 010 110 1150 - 3.5
NOTE
Below 850mV output setting De-emphasis gain is reduced.
NOTE
The DS100BR111A VOD for OUTPUT A is limited to 575 mV in pin mode (ENSMB=0).
With ENSMB = 1 or FLOAT, the VOD for OUTPUT A can be adjusted with SMBus register
0x23 [4:2] as shown in Table 8.
NOTE
In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the
DS100BR111A AD0-AD3 pins are internally forced to 0'h
Table 4. Signal Detect Threshold Level
(1)
SD_TH SMBus REG bit [3:2] and [1:0] Assert Level (Typical) De-assert Level (Typical)
0 10 210 mV 150 mV
20K to GND 01 160 mV 100 mV
Float (Default) 00 180 mV 110 mV
1 11 190 mV 130 mV
(1) VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps
12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS100BR111A