Datasheet
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28
27
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25
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21
20
GND
(PPAD)
VNEG
IN1
EN1
IN2
EN2
IN3
EN3
IN4
EN4
LGND
nFAULT
nSLEEP
nRESET
V3P3OUT
NC
VNEG
VM
NC
VNEG
OUT4
OUT2
OUT3
OUT1
VNEG
VCP
VM
CP1
CP2
DRV8844
SLVSBA2A –JULY 2012–REVISED OCTOBER 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted)
(1) (2)
VALUE UNIT
VM Power supply voltage range –0.3 to 65 V
Logic ground voltage range (LGND) –0.5 to VM - 8 V
Digital pin voltage range LGND - 0.5 to LGND + 7 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous motor drive output current
(3)
2.5 A
T
J
Operating virtual junction temperature range –40 to 150 °C
T
stg
Storage temperature range –60 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VNEG terminal, unless otherwise specified.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
DRV8844
THERMAL METRIC
(1)
PWP UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
31.6
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
15.9
θ
JB
Junction-to-board thermal resistance
(4)
5.6
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.2
ψ
JB
Junction-to-board characterization parameter
(6)
5.5
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
1.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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