Datasheet

1
xPHASE
xOUT1
xENBL
2
5
6
3
4
xOUT2
DRV8838
5
6
DRV8837, DRV8838
SLVSBA4C –JUNE 2012–REVISED FEBRUARY 2014 www.ti.com
6.6 Timing Requirements
T
A
= 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω
NUMBER PARAMETER TEST CONDITIONS MIN MAX UNIT
1 t
1
Delay time, PHASE high to OUT1 low 160 ns
2 t
2
Delay time, PHASE high to OUT2 high 200 ns
3 t
3
Delay time, PHASE low to OUT1 high 200 ns
4 t
4
Delay time, PHASE low to OUT2 low 160 ns
5 t
5
Delay time, ENBL high to OUTx high 200 ns
6 t
6
Delay time, ENBL low to OUTx low 160 ns
7 t
7
Output enable time 300 ns
8 t
8
Output disable time 300 ns
9 t
9
Delay time, INx high to OUTx high 160 ns
10 t
10
Delay time, INx low to OUTx low 160 ns
11 t
11
Output rise time 30 188 ns
12 t
12
Output fall time 30 188 ns
t
wake
Wake time, nSLEEP rising edge to part active 30 μs
Figure 1. Input and Output Timing for DRV8838
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