Datasheet

OUT 1

OUT2

VCC

IN2

Pre-

drive

VCC

PWM

OCP

IN1

VSET

Integrator

DIFF

COMP

DCM

ISEN

COMP

REF

ITRIP

DRV8832

www.ti.com

SLVSAB3H –MAY 2010–REVISED OCTOBER 2013

FUNCTIONAL DESCRIPTION

Power Supervisor

The DRV8832 is capable of entering a low-power sleep mode by bringing both of the INx control inputs logic low.

The outputs will be disabled Hi-Z.

In order to exit the sleep mode, bring either or both of the INx inputs logic high. This will enable the H-bridges.

When exiting the sleep mode, the FAULTn pin will pulse low.

PWM Motor Driver

The DRV8832 contains an H-bridge motor driver with PWM voltage-control circuitry with current limit circuitry. A

block diagram of the motor control circuitry is shown below.

Figure 3. Motor Control Circuitry

Bridge Control

The IN1 and IN2 control pins enable the H-bridge outputs. The following table shows the logic:

Table 2. H-Bridge Logic

IN1 IN2 OUT1 OUT2 Function

0 0 Z Z Sleep/Coast

0 1 L H Reverse

1 0 H L Forward

1 1 H H Brake

When both inputs are low, the output drivers are disabled and the device is placed into a low-power sleep state.

The current limit fault condition (if present) is also cleared. Note that when transitioning from either brake or sleep

mode to forward or reverse, the voltage control PWM starts at zero duty cycle. The duty cycle slowly ramps up to

the commanded voltage. This can take up to 12 ms to go from sleep to 100% duty cycle. Because of this, high-

speed PWM signals cannot be applied to the IN1 and IN2 pins. To control motor speed, use the VSET pin as

described below.

Product Folder Links: DRV8832