Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
28
27
26
2524
23
22
21
20
NC
AOUT1
VM
VM
AOUT2
AISEN
SCS
NC
RESETn
ABVREF
BISEN
CDVREF
TEST
SLEEPn
V3P3
BOUT2
BOUT1
SCLK
TEST
SDATA
SSTB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PGND
PGND
PGND
PGND
PGND
PGND
Solder these
pins to copper
heatsink area
PGND
PGND
PGND
PGND
PGND
VCP
CP2
CP1
VM
DOUT2
DISEN
DOUT1
VM
NC
NC
CISEN
COUT2
TEST
COUT1
TEST
PGND
Solder these
pins to copper
heatsink area
DRV8823
SLVS913D –JANUARY 2009–REVISED JANUARY 2010
www.ti.com
DCA PACKAGE
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
V
M
Power supply voltage range –0.3 to 34 V
V
I
Logic input voltage range
(3)
–0.5 to 5.75 V
I
O(peak)
Peak motor drive output current, t < 1 ms Internally limited
I
O
Motor drive output current
(4)
1.5 A
P
D
Continuous total power dissipation See Dissipation Ratings Table
T
J
Operating virtual junction temperature range –40 to 150 °C
T
A
Operating ambient temperature range –40 to 85 °C
T
stg
Storage temperature range –60 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Input pins may be driven in this voltage range regardless of presence or absence of V
M
.
(4) Power dissipation and thermal limits must be observed.
DISSIPATION RATINGS
DERATING FACTOR
BOARD PACKAGE R
qJA
T
A
< 25°C T
A
= 70°C T
A
= 85°C
ABOVE T
A
= 25°C
Low-K
(1)
75.7°C/W 13.2 mW/°C 1.65 W 1.06 W 0.86 W
Low-K
(2)
32°C/W 31.3 mW/°C 3.91 W 2.50 W 2.03 W
DCA
High-K
(3)
30.3°C/W 33 mW/°C 4.13 W 2.48 W 2.15 W
High-K
(4)
22.3°C/W 44.8 mW/°C 5.61 W 3.59 W 2.91 W
(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm
2
2-oz copper on back
side.
(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm
2
1-oz copper on back
side and solid 1-oz internal ground plane.
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