Datasheet

SCS
SCLK
SDATA
SSTB
D8 D9 D10 D11 D12 D13 D14 D15
Note 1
Note 2
D0 D1 D2 D3 D4 D5 D6 D7
DRV8823
www.ti.com SLVS913D –JANUARY 2009–REVISED JANUARY 2010
Data Format
Table 1. Motor 1 Command (Bridges A & B)
D15 -
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D12
ADDR
Name BDECAY B12 B11 B10 BPHASE BENBL ADECAY A12 A11 A10 APHASE AENBL
(= 0000)
Reset
x 0 0 0 0 0 0 0 0 0 0 0 0
Value
Table 2. Motor 2 Command (Bridges C & D)
D15 -
Bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D12
ADDR
Name DDECAY D12 D11 D10 DPHASE DENBL CDECAY C12 C11 C10 CPHASE CENBL
(= 0001)
Reset
x 0 0 0 0 0 0 0 0 0 0 0 0
Value
Serial Data Timing
Figure 4. Serial Data Timing Diagram
Note 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This
allows 8- or 16-bit transfers.
Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data will
continue to be shifted into the data register.
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