Datasheet
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ISENA
HOME
DIR
AOUT1
DECAY
RCA
GND
VREF
RCB
VCC
BOUT1
USM1
USM0
ISENB
VMA
SLEEPn
ENABLEn
AOUT2
CP2
CP1
VCP
GND
VGD
STEP
BOUT2
RESETn
SRn
VMB
GND
(PPAD)
DRV8818
SLVSAX9C –SEPTEMBER 2011–REVISED NOVEMBER 2013
www.ti.com
PWP (HTSSOP) PACKAGE
ABSOLUTE MAXIMUM RATINGS
(1) (2) (3)
MIN MAX UNIT
V
MX
Power supply voltage range –0.3 35 V
V
CC
Power supply voltage range –0.3 7 V
Digital pin voltage range –0.5 7 V
V
REF
Input voltage range –0.3 V V
CC
V
ISENSEx pin voltage range –0.3 0.5 V
I
O(peak)
Peak motor drive output current Internally limited
P
D
Continuous total power dissipation See Thermal Information table
T
J
Operating junction temperature range –40 150 °C
T
stg
Storage temperature range –60 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings " may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
DRV8818
THERMAL METRIC
(1)
PWP UNITS
28 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
32.2
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
16.3
θ
JB
Junction-to-board thermal resistance
(4)
14
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.5
ψ
JB
Junction-to-board characterization parameter
(6)
13.8
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
2.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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