Datasheet

DRV8803
SLVSAW5B –JULY 2011–REVISED FEBRUARY 2012 www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
VM Power supply voltage range –0.3 to 65 V
VOUTx Output voltage range –0.3 to 65 V
VCLAMP Clamp voltage range –0.3 to 65 V
nFAULT Output current 20 mA
Peak clamp diode current 2 A
DC or RMS clamp diode current 1 A
Digital input pin voltage range –0.5 to 7 V
nFAULT Digital output pin voltage range –0.5 to 7 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous total power dissipation See Dissipation Ratings table
T
J
Operating virtual junction temperature range –40 to 150 °C
T
stg
Storage temperature range –60 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8803 DRV8803
THERMAL METRIC DW PWP UNITS
20 PINS 16 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
67.7 39.6
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
32.9 24.6
θ
JB
Junction-to-board thermal resistance
(3)
35.4 20.3
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
8.2 0.7
ψ
JB
Junction-to-board characterization parameter
(5)
34.9 20.1
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
N/A 2.3
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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