Datasheet
DRV8800
DRV8801
SLVS855G –JULY 2008–REVISED OCTOBER 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VBB Load supply voltage
(2)
40 V
Output current 2.8 A
V
Sense
Sense voltage ±500 mV
VBB to OUTx 36 V
OUTx to SENSE 36 V
VDD Logic input voltage
(2)
–0.3 7 V
Human-Body Model (HBM) ±2 kV
ESD rating
Charged-Device Model (CDM) 500 V
Continuous total power dissipation See Dissipation Ratings Table
T
A
Operating free-air temperature range –40 85 °C
T
J
Maximum junction temperature 190 °C
T
stg
Storage temperature range –40 125 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8800/01 DRV8800/01
THERMAL METRIC RTY PWP UNITS
16 PINS 16 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
38.1 43.9
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
36.7 30.8
θ
JB
Junction-to-board thermal resistance
(3)
16.1 25.3
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
0.3 1.1
ψ
JB
Junction-to-board characterization parameter
(5)
16.2 25
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
4.1 5.6
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
IN
Input voltage, VBB 8 32 38 V
T
A
Operating free-air temperature –40 85 °C
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