Datasheet

DRV8800

DRV8801

www.ti.com

SLVS855G –JULY 2008–REVISED OCTOBER 2013

Control Logic Table

(1)

PINS

OPERATION

PHASE ENABLE MODE 1 MODE 2 nSLEEP OUT+ OUT-

1 1 X X 1 H L Forward

0 1 X X 1 L H Reverse

X 0 1 0 1 L L Brake (slow decay)

X 0 1 1 1 H H Brake (slow decay)

Fast-decay synchronous

1 0 0 X 1 L H

rectification

(2)

Fast-decay synchronous

0 0 0 X 1 H L

rectification

(2)

X X X X 0 Z Z Sleep mode

(1) X = Don’t care, Z = high impedance

(2) To prevent reversal of current during fast-decay synchronous rectification, outputs go to the high-impedance state as the current

approaches 0 A.

Overcurrent Protection

The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not

shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag nFAULT is driven

low, and a 1.2-ms fault timer is started. After this 1.2-ms period, t

OCP

, the device is then allowed to follow the

input commands and another turnon is attempted (nFAULT becomes high again during this attempt). If there is

still a fault condition, the cycle repeats. If after t

OCP

expires it is determined the short condition is not present,

normal operation resumes and nFAULT is deasserted.

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