Datasheet

Charge Pump
nFAULT
PHASE
GND
nSLEEP
ENABLE
OUT
SENSE
VCP
GND
CP2CP1
OUT
VBB
VBB
M
3.3K
.22 uf
.1 uf
.1 uf100 uf
.1 uf
VREG
MODE
Low-Side
Gate Supply
Control
Logic
Motor lead
Protection
Bias
Supply
PAD
VDD
3.3K
VBB
OUT+
OUT
-
SENSE
UVLO
STB
STG
TSD
Optional
+
-
DRV8800
DRV8801
SLVS855G –JULY 2008–REVISED OCTOBER 2013 www.ti.com
Figure 3. DRV8800 FUNCTIONAL BLOCK DIAGRAM
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