Datasheet

DRV8412
DRV8432
www.ti.com SLES242C –DECEMBER 2009–REVISED MAY 2010
PACKAGE HEAT DISSIPATION RATINGS
PARAMETER DRV8412 DRV8432
R
qJC
, junction-to-case (power pad / heat slug) thermal
1.1 °C/W 0.9 °C/W
resistance
This device is not intended to be used without a
R
qJA
, junction-to-ambient thermal resistance 25 °C/W heatsink. Therefore, R
qJA
is not specified. See the
Thermal Information section.
Exposed power pad / heat slug area 34 mm
2
80 mm
2
PACKAGE POWER DERATINGS (DRV8412)
(1)
DERATING
T
A
= 25°C
FACTOR T
A
= 70°C POWER T
A
= 85°C POWER T
A
= 125°C POWER
PACKAGE POWER
ABOVE T
A
= RATING RATING RATING
RATING
25°C
44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W 1.0 W
(1) Based on EVM board layout
MODE SELECTION PINS
MODE PINS
OUTPUT
DESCRIPTION
CONFIGURATION
M3 M2 M1
Dual full bridges (two PWM inputs each full bridge) or four half bridges with
0 0 0 2 FB or 4 HB
cycle-by-cycle current limit
Dual full bridges (two PWM inputs each full bridge) or four half bridges with
0 0 1 2 FB or 4 HB
OC latching shutdown (no cycle-by-cycle current limit)
0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit
Dual full bridges (one PWM input each full bridge with complementary PWM
0 1 1 2 FB
on second half bridge) with cycle-by-cycle current limit
1 x x Reserved
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Product Folder Link(s): DRV8412 DRV8432