Datasheet

DRV8412
DRV8432
SLES242C –DECEMBER 2009–REVISED MAY 2010 www.ti.com
Overtemperature Protection
Figure 6 illustrates cycle-by-cycle operation with high
side OC event and Figure 7 shows cycle-by-cycle
The DRV8412/32 have a two-level
operation with low side OC. Dashed lines are the
temperature-protection system that asserts an
operation waveforms when no CBC event is triggered
active-low warning signal (OTW) when the device
and solide lines show the waveforms when CBC
junction temperature exceeds 125°C (nominal) and, if
event is triggered. In CBC current limiting mode,
the device junction temperature exceeds 150°C
when low side FET OC is detected, devcie will turn
(nominal), the device is put into thermal shutdown,
off the affected low side FET and keep the high side
resulting in all half-bridge outputs being set in the
FET at the same half brdige off until next PWM cycle;
high-impedance (Hi-Z) state and FAULT being
when high side FET OC is detected, devcie will turn
asserted low. OTSD is latched in this case and
off the affected high side FET and turn on the low
RESET_AB and RESET_CD must be asserted low to
side FET at the half brdige until next PWM cycle.
clear the latch.
In OC latching shut down mode, the CBC current limit
Undervoltage Protection (UVP) and Power-On
and error recovery circuitries are disabled and an
Reset (POR)
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_AB
The UVP and POR circuits of the DRV8412/32 fully
and/or RESET_CD must be asserted to restore
protect the device in any power-up/down and
normal operation after the overcurrent condition is
brownout situation. While powering up, the POR
removed.
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
For added flexibility, the OC threshold is
and VDD supply voltages reach 9.8 V (typical).
programmable using a single external resistor
Although GVDD_X and VDD are independently
connected between the OC_ADJ pin and GND pin.
monitored, a supply voltage drop below the UVP
See Table 2 for information on the correlation
threshold on any VDD or GVDD_X pin results in all
between programming-resistor value and the OC
half-bridge outputs immediately being set in the
threshold. It should be noted that a properly
high-impedance (Hi-Z) state and FAULT being
functioning overcurrent detector assumes the
asserted low. The device automatically resumes
presence of a proper inductor or power ferrite bead at
operation when all supply voltage on the bootstrap
the power-stage output. Short-circuit protection is not
capacitors have increased above the UVP threshold.
guaranteed with direct short at the output pins of the
power stage.
DEVICE RESET
Table 2. Programming-Resistor Values and OC
Two reset pins are provided for independent control
Threshold
of half-bridges A/B and C/D. When RESET_AB is
OC-ADJUST RESISTOR MAXIMUM CURRENT BEFORE
asserted low, all four power-stage FETs in
VALUES (kΩ) OC OCCURS (A)
half-bridges A and B are forced into a
22
(1)
11.6
high-impedance (Hi-Z) state. Likewise, asserting
RESET_CD low forces all four power-stage FETs in
24 10.7
half-bridges C and D into a high- impedance state. To
27 9.7
accommodate bootstrap charging prior to switching
30 8.8
start, asserting the reset inputs low enables weak
36 7.4
pulldown of the half-bridge outputs.
39 6.9
A rising-edge transition on reset input allows the
43 6.3
device to resume operation after a shut-down fault.
47 5.8
E.g., when either or both half-bridge A and B have
56 4.9
OC shutdown, a low to high transition of RESET_AB
pin will clear the fault and FAULT pin; when either or
68 4.1
both half-bridge C and D have OC shutdown, a low to
82 3.4
high transition of RESET_CD pin will clear the fault
100 2.8
and FAULT pin as well. When an OTSD occurs, both
120 2.4
RESET_AB and RESET_CD need to have a low to
150 1.9
high transition to clear the fault and FAULT signal.
200 1.4
(1) Recommended to use in OC Latching Mode Only
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