Datasheet

Not Recommended for New Designs
DRV8402
www.ti.com SLES222 –FEBRUARY 2009
THEORY OF OPERATION
Special attention should be paid to the power-stage
POWER SUPPLIES
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
To help with system design, the DRV8402 needs only
half-bridge has independent power-stage supply pins
a 12 V supply in addition to power-stage supply. An
(PVDD_X). For optimal electrical performance, EMI
internal voltage regulator provides suitable voltage
compliance, and system reliability, it is important that
levels for the digital and low-voltage analog circuitry.
each PVDD_X pin is decoupled with a ceramic
Additionally, all circuitry requiring a floating voltage
capacitor placed as close as possible to each supply
supply, for example, the high-side gate drive, is
pin. It is recommended to follow the PCB layout of
accommodated by built-in bootstrap circuitry requiring
the DRV8402 in EVM board.
only a few external capacitors.
The 12 V supply should be from a low-noise,
To provide electrical characteristics, the PWM signal
low-output-impedance voltage regulator. Likewise, the
path including gate drive and output stage is
50 V power-stage supply is assumed to have low
designed as identical, independent half-bridges. For
output impedance and low noise. The power-supply
this reason, each half-bridge has separate gate drive
sequence is not critical as facilitated by the internal
supply (GVDD_X), bootstrap pins (BST_X), and
power-on-reset circuit. Moreover, the DRV8402 is
power-stage supply pins (PVDD_X). Furthermore, an
fully protected against erroneous power-stage turn-on
additional pin (VDD) is provided as supply for all
due to parasitic gate charging. Thus, voltage-supply
common circuits. Although supplied from the same
ramp rates (dv/dt) are non-critical within the specified
12-V source, it is recommended that a 1 – 10 Ω
range (see the Recommended Operating Conditions
resistor is used to separate the GVDD_X pins from
section of this data sheet).
VDD on the printed-circuit board (PCB). Special
attention should be paid to placing all decoupling
capacitors as close to their associated pins as SYSTEM POWER-UP/POWER-DOWN
possible. In general, inductance between the power SEQUENCE
supply pins and decoupling capacitors must be
avoided. Powering Up
For a properly functioning bootstrap circuit, a small The DRV8402 does not require a power-up
ceramic capacitor must be connected from each sequence. The outputs of the H-bridges remain in a
bootstrap pin (BST_X) to the power-stage output pin high-impedance state until the gate-drive supply
(OUT_X). When the power-stage output is low, the voltage (GVDD_X) and VDD voltage are above the
bootstrap capacitor is charged through an internal undervoltage protection (UVP) voltage threshold (see
diode connected between the gate-drive the Electrical Characteristics section of this data
power-supply pin (GVDD_X) and the bootstrap pin. sheet). Although not specifically required, holding
When the power-stage output is high, the bootstrap RESET_AB and RESET_CD in a low state while
capacitor potential is shifted above the output powering up the device is recommended. This allows
potential and thus provides a suitable voltage supply an internal circuit to charge the external bootstrap
for the high-side gate driver. In an application with capacitors by enabling a weak pulldown of the
PWM switching frequencies in the range from 25 kHz half-bridge output (except in half-bridge modes).
to 500 kHz, the use of 47 nF ceramic capacitors, size
0603 or 0805, is recommended for the bootstrap Powering Down
supply. These 47 nF capacitors ensure sufficient
The DRV8402 does not require a power-down
energy storage, even during minimal PWM duty
sequence. The device remains fully operational as
cycles, to keep the high-side power stage FET fully
long as the gate-drive supply (GVDD_X) voltage and
turned on during the remaining part of the PWM
VDD voltage are above the UVP voltage threshold
cycle. In an application running at a switching
(see the Electrical Characteristics section of this data
frequency lower than 25 kHz, the bootstrap capacitor
sheet). Although not specifically required, it is a good
might need to be increased in value.
practice to hold RESET_AB and RESET_CD low
during power down to prevent any unknown state
during this transition.
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