Datasheet

Not Recommended for New Designs
DRV8402
SLES222 –FEBRUARY 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
Ta = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, F
Sw
= 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
V
REG
VDD = 12 V 2.95 3.3 3.65 V
reference node
I
VDD
VDD supply current Idle, reset mode 9 12 mA
I
GVDD_X
Gate supply current per half-bridge Reset mode 1.7 2 mA
I
PVDD_X
Half-bridge X (A, B, C, or D) idle current Reset mode 0.5 1 mA
Output Stage
MOSFET drain-to-source resistance, low T
J
= 25°C, includes metallization resistance,
90 mΩ
side (LS) GVDD = 12 V
R
DS(on)
MOSFET drain-to-source resistance, high T
J
= 25°C, includes metallization resistance,
90 mΩ
side (HS) GVDD = 12 V
V
F
Diode forward voltage drop T
J
= 25°C - 125°C, I
O
= 5 A 1 V
t
R
Output rise time Resistive load, I
O
= 5 A 9 nS
t
F
Output fall time Resistive load, I
O
= 5 A 9 nS
t
PD_ON
Propagation delay when FET is on Resistive load, I
O
= 5 A 42 nS
t
PD_OFF
Propagation delay when FET is off Resistive load, I
O
= 5 A 40 nS
t
DT
Dead time between HS and LS FETs Resistive load, I
O
= 5 A 5 nS
I/O Protection
Gate supply voltage GVDD_X
V
uvp,G
8.5 V
undervoltage protection
Hysteresis for gate supply undervoltage
V
uvp,hyst
(1)
0.8 V
event
OTW
(1)
Overtemperature warning 115 125 135 °C
Hysteresis temperature to reset OTW
OTW
hyst
(1)
25 °C
event
OTSD
(1)
Overtemperature shut down 150 °C
OTE-OTW
differential
OTE-OTW overtemperature detect
25 °C
(1)
temperature difference
Hysteresis temperature for FAULT to be
OTSD
HYST
(1)
25 °C
released following an OTSD event.
I
OC
Overcurrent limit protection Resistor—programmable, nominal, R
OCP
= 27 kΩ 10.6 A
Time from application of short condition to Hi-Z of
I
OCT
Overcurrent response time 250 ns
affected FET(s)
Connected when RESET_AB or RESET_CD is
Internal pulldown resistor at the output of
R
PD
active to provide bootstrap capacitor charge. Not 1 kΩ
each half-bridge
used in SE mode
Static Digital Specifications
V
IH
High-level input voltage 2 V
PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3,
RESET_AB, RESET_CD
V
IL
Low-level input voltage 0.8 V
l
lkg
Input leakage current -100 100 μA
OTW / FAULT
Internal pullup resistance, OTW to
R
INT_PU
20 26 35 kΩ
VREG, FAULT to VREG
Internal pullup resistor only 2.95 3.3 3.65
V
OH
High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
V
OL
Low-level output voltage I
O
= 4 mA 0.2 0.4 V
(1) Specified by design
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