Datasheet
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GVDD_B
OTW
FAULT
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
VDD
GVDD_C
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
BST_D
GVDD_D
Not Recommended for New Designs
DRV8402
www.ti.com
SLES222 –FEBRUARY 2009
DEVICE INFORMATION
Pin Assignment
The DRV8402 is available in a thermally enhanced package:
• 36-pin PSOP3 package (DKD)
This package contains a heat slug that is located on the top side of the device for convenient thermal coupling to
the heatsink.
DKD PACKAGE
(TOP VIEW)
MODE Selection Pins
MODE PINS
OUTPUT
DESCRIPTION
CONFIGURATION
M3 M2 M1
0 0 0 2 FB Dual full bridge with cycle-by-cycle current limit
0 0 1 2 FB Dual full bridge with OC latching shutdown (no cycle-by-cycle current limit)
0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit
0 1 1 1 PFB Parallel full bridge with OC latching shutdown
Half bridge with cycle-by-cycle current limit. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
1 0 0 4 HB
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
1 0 1 Half bridge with OC latching shutdown. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
4 HB
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
1 1 0
Reserved
1 1 1
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Product Folder Link(s): DRV8402