Datasheet

Not Recommended for New Designs
DRV8402
www.ti.com SLES222 –FEBRUARY 2009
Undervoltage Protection (UVP) and Power-On
For added flexibility, the OC threshold is
Reset (POR)
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
The UVP and POR circuits of the DRV8402 fully
and AGND pin. See Table 2 for information on the
protect the device in any power-up/down and
correlation between programming-resistor value and
brownout situation. While powering up, the POR
the OC threshold. It should be noted that a properly
circuit resets the overcurrent circuit and ensures that
functioning overcurrent detector assumes the
all circuits are fully operational when the GVDD_X
presence of a proper inductor at the power-stage
and VDD supply voltages reach 9.8 V (typical).
output (minimum 2 μH). Short-circuit protection is not
Although GVDD_X and VDD are independently
provided directly at the output pins of the power
monitored, a supply voltage drop below the UVP
stage, but only after the inductor. If a further smaller
threshold on any VDD or GVDD_X pin results in all
inductor is preferred for any reason, using OCL mode
half-bridge outputs immediately being set in the
setting is recommended.
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
Table 2.
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
OC-Adjust Resistor Values Max. Current Before OC Occurs
(kΩ) (A)
22
(1)
12.2
DEVICE RESET
24
(1)
11.5
Two reset pins are provided for independent control
27 10.6
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in
30 9.9
half-bridges A and B are forced into a
33 9.3
high-impedance (Hi-Z) state. Likewise, asserting
36 8.7
RESET_CD low forces all four power-stage FETs in
39 8.2
half-bridges C and D into a high-impedance state.
In full bridge and parallel full bridge configurations, to
Overtemperature Protection
accommodate bootstrap charging prior to switching
The DRV8402 has a two-level temperature-protection
start, asserting the reset inputs low enables weak
system that asserts an active-low warning signal
pulldown of the half-bridge outputs. In half bridge
(OTW) when the device junction temperature
configuration, the weak pulldowns are not enabled,
exceeds 125°C (nominal) and, if the device junction
and it is, therefore, recommended to precharge
temperature exceeds 150°C (nominal), the device is
bootstrap capacitor by providing a low pulse on the
put into thermal shutdown, resulting in all half-bridge
PWM inputs first when reset is asserted high.
outputs being set in the high-impedance (Hi-Z) state
Asserting either reset input low removes any fault
and FAULT being asserted low. OTSD is latched in
information to be signaled on the FAULT output, i.e.,
this case and RESET_AB and RESET_CD must be
FAULT is forced high.
asserted low.
A rising-edge transition on either reset input allows
the device to resume operation after an overcurrent
(1) Recommended to use in OCL Mode Only fault.
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