Datasheet

Not Recommended for New Designs
DRV8402
SLES222 –FEBRUARY 2009 www.ti.com
Bootstrap Capacitor Under Voltage Protection
ERROR REPORTING
When the device runs at a low switching frequency
The FAULT and OTW pins are both active-low,
(e.g. less than 20 kHz with 47 nF bootstrap
open-drain outputs. Their function is for
capacitor), the bootstrap capacitor voltage might not
protection-mode signaling to a PWM controller or
be able to maintain a proper voltage level for the
other system-control device.
high-side gate driver. A bootstrap capacitor
Any fault resulting in device shutdown is signaled by
undervoltage protection circuit (BST_UVP) will start
the FAULT pin going low. Likewise, OTW goes low
under this circumstance to prevent the potential
when the device junction temperature exceeds 125°C
failure of the high-side MOSFET. When the voltage
(see Table 1).
on the bootstrap capacitors is less than required for
safe operation, the DRV8402 will initiate bootstrap
Table 1.
capacitor recharge sequences (turn off high side FET
for a short period) until the bootstrap capacitors are
FAULT OTW DESCRIPTION
properly charged for safe operation. This function
0 0 Overtemperature warning and
may also be activated when PWM duty cycle is too
(overtemperature shut down or overcurrent
shut down or undervoltage protection)
high (e.g. higher than 99.5%). Note that bootstrap
occurred
capacitor might not be able to be charged up if no
0 1 Overcurrent shut-down or undervoltage
load is presented at output.
protection occurred
Because the extra pulse width to charge bootstrap
1 0 Overtemperature warning
capacitor is so short, that the output current
1 1 Device under normal operation
disruption due to the extra charge is negligible most
of the time when output inductor is present.
Note that asserting either RESET_AB or RESET_CD
low forces the FAULT signal high, independent of
Overcurrent (OC) Protection
faults being present. For proper error reporting, set
both RESET_AB and RESET_CD high during normal
The device has independent, fast-reacting current
operation.
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
TI recommends monitoring the OTW signal using the
FETs. There are two settings for OC protection
system microcontroller and responding to an OTW
through Mode selection pins: cycle-by-cycle (CBC)
signal by reducing the load current to prevent further
current limiting mode and OC latching (OCL) shut
heating of the device resulting in device
down mode.
overtemperature shutdown (OTSD).
In CBC current limiting mode, the detector outputs
To reduce external component count, an internal
are monitored by two protection systems. The first
pullup resistor to 3.3 V is provided on both FAULT
protection system controls the power stage in order to
and OTW outputs. Level compliance for 5-V logic can
prevent the output current from further increasing,
be obtained by adding external pull-up resistors to 5
i.e., it performs a CBC current-limiting function rather
V (see the Electrical Characteristics section of this
than prematurely shutting down the device. This
data sheet for further specifications).
feature could effectively limit the inrush current during
motor start-up or transient without damaging the
DEVICE PROTECTION SYSTEM
device. During short to power and short to ground
condition, the current limit circuitry might not be able
The DRV8402 contains advanced protection circuitry
to control the current in a proper level, a second
carefully designed to facilitate system integration and
protection system triggers a latching shutdown,
ease of use, as well as to safeguard the device from
resulting in the power stage being set in the
permanent failure due to a wide range of fault
high-impedance (Hi-Z) state. Current limiting and
conditions such as short circuits, overcurrent,
overcurrent protection are independent for
overtemperature, and undervoltage. The DRV8402
half-bridges A, B, C, and, D, respectively.
responds to a fault by immediately setting the power
stage in a high-impedance (Hi-Z) state and asserting
In OCL shut down mode, the cycle-by-cycle current
the FAULT pin low. In situations other than
limit and error recovery circuitry is disabled and an
overcurrent or overtemperature, the device
overcurrent condition will cause the device to
automatically recovers when the fault condition has
shutdown immediately. After shutdown, RESET_AB
been removed or the gate supply voltage has
and/or RESET_CD must be asserted to restore
increased. For highest possible reliability, recovering
normal operation after the overcurrent condition is
from an overcurrent shut down (OCSD) or OTSD fault
removed.
requires external reset of the device (see the Device
Reset section of this data sheet) no sooner than 1
second after the shutdown.
10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DRV8402