Datasheet

B1
C37
C33
T1
T2
T3
T4
C46
C43
DRV8312
DRV8332
SLES256C –MAY 2010–REVISED OCTOBER 2013 www.ti.com
T1: PVDD decoupling capacitors C37, C43, and C46 should be placed very close to PVDD_X pins and ground return
path.
T2: VREG decoupling capacitor C33 should be placed very close to VREG abd AGND pins.
T3: Clear the space above and below the device as much as possible to improve the thermal spreading.
T4: Add many vias to reduce the impedance of ground path through top to bottom side. Make traces as wide as
possible for ground path such as GND_X path.
Figure 14. Printed Circuit Board – Top Layer
B1: Do not block the heat transfer path at bottom side. Clear as much space as possible for better heat spreading.
Figure 15. Printed Circuit Board – Bottom Layer
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