Datasheet

PWM_HS
PWM_LS
Load
Current
CurrentLimit
T_HS
T_OC
PVDD
GND_X
PWM_HS
PWM_LS
Load
T_LS
CBCwithHighSideOC
DuringT_OCPeriod
DRV8312
DRV8332
www.ti.com SLES256C –MAY 2010–REVISED OCTOBER 2013
DIFFERENT OPERATIONAL MODES Figure 11 shows six steps trapezoidal scheme with
hall sensor control and Figure 12 shows six steps
The DRV8312/32 support two different modes of
trapezoidal scheme with sensorless control. The hall
operation:
sensor sequence in real application might be different
1. Three-phase (3PH) or three half bridges (HB)
than the one we showed in Figure 11 depending on
with CBC current limit
the motor used. Please check motor manufacture
datasheet for the right sequence in applications. In
2. Three-phase or three half bridges with OC
six step trapezoidal complementary control scheme, a
latching shutdown (no CBC current limit)
half bridge with larger than 50% duty cycle will have a
positive current and a half bridge with less than 50%
Because each half bridge has independent supply
duty cycle will have a negative current. For normal
and ground pins, a shunt sensing resistor can be
operation, changing PWM duty cycle from 50% to
inserted between PVDD to PVDD_X or GND_X to
100% will adjust the current from 0 to maximum value
GND (ground plane). A high side shunt resistor
with six steps control. It is recommanded to apply a
between PVDD and PVDD_X is recommended for
minimum 50ns to 100 nS PWM pulse at each
differential current sensing because a high bias
switching cycle at lower side to properly charge the
voltage on the low side sensing could affect device
bootstrap cap. The impact of minimum pulse at low
operation. If low side sensing has to be used, a shunt
side FET is pretty small, e.g., the maximum duty
resistor value of 10 mΩ or less or sense voltage 100
cycle is 99.9% with 100ns minimum pulse on low
mV or less is recommended.
side. RESET_Xpin can be used to get channel X into
Figure 8 and Figure 9 show the three-phase
high impedance mode. If you prefer PWM switching
application examples, and Figure 10 shows how to
one channel but hold low side FET of the other
connect to DRV8312/32 with some simple logic to
channel on (and third channel in Hi-Z) for 2-quadrant
accommodate conventional 6 PWM inputs control.
mode, OT latching shutdown mode is recommended
to prevent the channel with low side FET on stuck in
We recommend using complementary control
Hi-Z during OC event in CBC mode.
scheme for switching phases to prevent circulated
energy flowing inside the phases and to make current
The DRV8312/32 can also be used for sinusoidal
limiting feature active all the time. Complementary
waveform control and field oriented control. Please
control scheme also forces the current flowing
check TI website MCU motor control library for
through sense resistors all the time to have a better
control algorithms.
current sensing and control of the system.
Figure 6. Cycle-by-Cycle Operation with High Side OC (dashed line: normal operation; solid line: CBC
event)
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