Datasheet

DRV8312
DRV8332
SLES256C –MAY 2010–REVISED OCTOBER 2013 www.ti.com
Figure 6 illustrates cycle-by-cycle operation with high It should be noted that a properly functioning
side OC event and Figure 7 shows cycle-by-cycle overcurrent detector assumes the presence of a
operation with low side OC. Dashed lines are the proper inductor or power ferrite bead at the power-
operation waveforms when no CBC event is triggered stage output. Short-circuit protection is not
and solide lines show the waveforms when CBC guaranteed with direct short at the output pins of the
event is triggered. In CBC current limiting mode, power stage.
when low side FET OC is detected, devcie will turn
off the affected low side FET and keep the high side Overtemperature Protection
FET at the same half brdige off until next PWM cycle;
The DRV8312/32 have a two-level temperature-
when high side FET OC is detected, devcie will turn
protection system that asserts an active-low warning
off the affected high side FET and turn on the low
signal (OTW) when the device junction temperature
side FET at the half brdige until next PWM cycle.
exceeds 125°C (nominal) and, if the device junction
In OC latching shut down mode, the CBC current limit temperature exceeds 150°C (nominal), the device is
and error recovery circuitries are disabled and an put into thermal shutdown, resulting in all half-bridge
overcurrent condition will cause the device to outputs being set in the high-impedance (Hi-Z) state
shutdown. After shutdown, RESET_A, RESET_B, and FAULT being asserted low. OTSD is latched in
and RESET_C must be asserted to restore normal this case and RESET_A, RESET_B, and RESET_C
operation after the overcurrent condition is removed. must be asserted low to clear the latch.
For added flexibility, the OC threshold is
Undervoltage Protection (UVP) and Power-On
programmable using a single external resistor
Reset (POR)
connected between the OC_ADJ pin and AGND pin.
The UVP and POR circuits of the DRV8312/32 fully
See Table 2 for information on the correlation
protect the device in any power-up / down and
between programming-resistor value and the OC
brownout situation. While powering up, the POR
threshold.
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
Table 2. Programming-Resistor Values and OC
Threshold and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
OC-ADJUST RESISTOR MAXIMUM CURRENT BEFORE
monitored, a supply voltage drop below the UVP
VALUES (kΩ) OC OCCURS (A)
threshold on any VDD or GVDD_X pin results in all
19
(1)
13.2
half-bridge outputs immediately being set in the high-
22 11.6
impedance (Hi-Z) state and FAULT being asserted
24 10.7
low. The device automatically resumes operation
when all supply voltage on the bootstrap capacitors
27 9.7
have increased above the UVP threshold.
30 8.8
36 7.4
DEVICE RESET
39 6.9
Three reset pins are provided for independent control
43 6.3
of half-bridges A, B, and C. When RESET_X is
47 5.8
asserted low, two power-stage FETs in half-bridges X
56 4.9
are forced into a high-impedance (Hi-Z) state.
68 4.1
A rising-edge transition on reset input allows the
82 3.4
device to resume operation after a shut-down fault.
100 2.8
That is, when half-bridge X has OC shutdown in CBC
120 2.4
mode, a low to high transition of RESET_X pin will
clear the fault and FAULT pin. When an OTSD or OC
150 1.9
shutdown in Latching mode occurs, all three
200 1.4
RESET_A, RESET_B, and RESET_C need to have a
low to high transition to clear the fault and reset
(1) Recommended to use in OC Latching Mode Only FAULT signal.
12 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DRV8312 DRV8332