Datasheet

DRV8312
DRV8332
www.ti.com SLES256D –MAY 2010–REVISED JANUARY 2014
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
PVDD_X Half bridge X (A, B, or C) DC supply voltage 0 50 52.5 V
GVDD_X Supply for logic regulators and gate-drive circuitry 10.8 12 13.2 V
VDD Digital regulator supply voltage 10.8 12 13.2 V
I
O_PULSE
Pulsed peak current per output pin (could be limited by thermal) 15 A
I
O
Continuous current per output pin (DRV8332) 8 A
F
SW
PWM switching frequency 500 kHz
R
OCP_CBC
OC programming resistor range in cycle-by-cycle current limit modes 22 200 kΩ
R
OCP_OCL
OC programming resistor range in OC latching shutdown modes 19 200 kΩ
C
BST
Bootstrap capacitor range 33 220 nF
t
ON_MIN
Minimum PWM pulse duration, low side, for charging the Bootstrap capacitor 50 ns
T
A
Operating ambient temperature -40 85
(1)
°C
(1) Depending on power dissipation and heat-sinking, the DRV8312/32 can support ambient temperature in excess of 85°C. Refer to the
package heat dissipation ratings table and package power deratings table.
PACKAGE HEAT DISSIPATION RATINGS
PARAMETER DRV8312 DRV8332
R
θJC
, junction-to-case (power pad / heat slug)
1.1 °C/W 0.9 °C/W
thermal resistance
This device is not intended to be used
without a heatsink. Therefore, R
θJA
is not
R
θJA
, junction-to-ambient thermal resistance 25 °C/W
specified. See the Thermal Information
section.
Exposed power pad / heat slug area 34 mm
2
80 mm
2
PACKAGE POWER DERATINGS (DRV8312)
(1)
DERATING
T
A
= 25°C
FACTOR T
A
= 70°C POWER T
A
= 85°C POWER T
A
= 125°C POWER
PACKAGE POWER
ABOVE T
A
= RATING RATING RATING
RATING
25°C
44-PIN TSSOP (DDW) 5.0 W 40.0 mW/°C 3.2 W 2.6 W 1.0 W
(1) Based on EVM board layout
MODE SELECTION PINS
MODE PINS
OUTPUT
DESCRIPTION
CONFIGURATION
M3 M2 M1
1 0 0 1 3PH or 3 HB Three-phase or three half bridges with cycle-by-cycle current limit
Three-phase or three half bridges with OC latching shutdown (no cycle-by-
1 0 1 1 3PH or 3 HB
cycle current limit)
0 x x Reserved
1 1 x Reserved
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